Lazy Data Routing And Greedy Scheduling For Application-specific Signal Processors

Rimey, Ken; Hilfinger, Paul

doi:10.1109/micro.1988.639268

Cited by 16 publications

(13 citation statements)

References 2 publications

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“…This aims at efficient handling of irregular data paths as frequently encountered for DSPs, where tight coupling of code generation phases is a must. A similar approach has also been developed by Rimey and Hilfinger [108]. The CBC data router is driven by a list scheduler and tries to avoid expensive spilling of special-purpose registers on the fly.…”

Section: Mem The_memory[1024int(16)]mentioning

confidence: 99%

Retargetable Compiler Technology for Embedded Systems

Leupers

Marwedel

2001

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Section: Mem The_memory[1024int(16)]mentioning

confidence: 99%

Retargetable Compiler Technology for Embedded Systems

Leupers

Marwedel

2001

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“…In contrast, the register combiner architecture directly connects some functional-unit outputs to other functional-unit inputs. Some application-specific signal processor architectures also have this property [16].…”

Section: Instruction Selection (Creating a Dag Of Register-to-registementioning

confidence: 99%

Compiling to a VLIW fragment pipeline

Mark

Proudfoot

2001

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware

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The latest generation of graphics hardware supports fully programmable vertex and pixel/fragment operations, but programming this hardware at a low level is difficult and time consuming. To address this problem, we have developed a complete real-time procedural shading system that compiles a high-level shading language to programmable vertex and fragment hardware, as described in a separate publication. In this paper, we describe in detail the algorithms used by this system to generate and optimize fragment code for NVIDIA's register combiner architecture and show that our compiler generates efficient code. The register combiner architecture has some similarities to VLIW CPU architectures, so we compare our compilation algorithms to those described in the literature for VLIW CPU architectures. We also discuss some of the lessons we learned from building and using this compiler that may be useful to the designers of future programmable graphics hardware.

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“…A phase called combiner only tries to concatenate adjacent operations. The work of Rimey [31,32] describes a compiler for application-specific DSPs. The main attention, however, is paid to scheduling and data-routing (i.e.…”

Section: Related Workmentioning

confidence: 99%

“…The goal of scheduling is minimum execution time for a given algorithm on an architecture which is fixed at compile-time. Therefore, the assignment of registers to intermediate values, the generation of data-routes (including spill-code) and scheduling are performed in parallel [23,32]. …”

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confidence: 99%

Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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Abstract. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. IntroductionIn the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators. OverviewIn the next section we will shortly discuss several related approaches to code generation and point out some differences of our system. Section 3 introduces the overall architecture and functionality of the CBC code generator. Section 4 explains the code selection task and the basic techniques used. In section 5 our algorithm is presented. We conclude the paper with experimental results. Points of major differences between our code selection approach and similar tasks in "classic" code generation (CG) are: -Complexity of datapaths. CBC has to deal with highly specialized and optimized datapaths. The hardware units make the efficient execution of frequently used operation sequences possible. Operation patterns for the functional units of these datapaths are much more complex than for standard microprocessors.-Type-handling. DSP algorithms may employ a large variety of different word lengths and numerical types. The hardware operators are restricted to fixed word lengths. A correct mapping must always be found. In most CG work this topic is neglected because language definitions (and hence the compilers) are restricted to "implementation-dependent" types. -Evaluation order. Approaches like [6,7] dealing with code selection assume a fixed evaluation order, which is usually derived from the imperative source code. There is no explicit scheduling phase included in the back-ends. Commonly, register allocation is performed during code selection. Most of the time this is done by graph coloring [4] or "on-the-fly".Parallelism of functional blocks. Most DSP architectures contain several functional units that work in parallel. Therefore, the final code cannot be emitted during or immediately after the code selection phase because partial instructions must be "compacted" into complete instructions at a later stage of compilation exploiting the possible para...

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Lazy Data Routing And Greedy Scheduling For Application-specific Signal Processors

Cited by 16 publications

References 2 publications

Retargetable Compiler Technology for Embedded Systems

Retargetable Compiler Technology for Embedded Systems

Compiling to a VLIW fragment pipeline

Global code selection for directed acyclic graphs

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