Layout pattern risk assessment in advanced technology node: methodology for pattern clustering and classification

Abstract

Due to insufficient lithographic margin, design rule based layout patterns can become killer defects on silicon such as necking and bridging. These may cause severe yield loss and progressive failure. This paper presents a weak pattern analysis methodology to improve process margin by eliminating risk factors at physical design level. We applied this method to the Back End of Line (BEOL) layers of 10nm class DRAM device. The concept of our algorithm is clustering similar patterns using Process Skew-Based Edge Tolerance (PSBET) of layout patterns. The clustered layout clips are analyzed through the After Development Inspection (ADI) contour simulation, and we design weak patterns on the Test Element Group (TEG) chip to check for actual defects. With our proposed method, we extracted layout clips from millions patterns of a full chip and categorized patterns of failure by 5 groups. Finally, we identified that the weak patterns detected by layout analysis methodology were 56% consistent with the defects detected on the wafer. We demonstrated that patterns with low process margin could be detected prior to mask tape-out. To prevent generation of weak patterns, we enhance layout design-rule coverage and build a hotspot library to gather data. This flow of pattern classification and hotspot detection is expected to be applied in sub-10nm DRAM and logic devices.