Layout-dependent aging mitigation for critical path timing

Hsu, Che-Lun; Guo, Shaofeng; Lin, Yibo; Xu, Xiaoqing; Li, Meng; Wang, Runsheng; Huang, Ru; Pan, David Z.

doi:10.1109/aspdac.2018.8297298

Cited by 5 publications

(2 citation statements)

References 18 publications

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“…Gate sizing [55,64] and pin-reordering/logic restructuring [68] are also implemented to minimize BTI effects. At the physical design level, Hsu et al [29] proposed a layout-dependent aging mitigation framework for critical path timing during standard cell placement stage and [81] introduced aging-aware FPGA placement. Gate replacement techniques were used in [65] to co-optimize circuit aging and leakage.…”

Section: Device Agingmentioning

confidence: 99%

Dealing with Aging and Yield in Scaled Technologies

Alawieh

Hsu

et al. 2020

Dependable Embedded Systems

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This chapter reviews recent practices of tackling aging and yield issues in VLSI design related to shrinking technology processes. Different fundamental effects such as device aging, interconnect electromigration, and process variations are investigated with the state-of-the-art techniques for modeling and optimization. The presented techniques vary from analytical approaches to machine learning, and often require cross-layer information feedback for robust design cycles.

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Section: Device Agingmentioning

confidence: 99%

Dealing with Aging and Yield in Scaled Technologies

Alawieh

Hsu

et al. 2020

Dependable Embedded Systems

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“…Aging jeopardizes device reliability by leading the device to early malfunctions. To address such reliability concerns, different aging-mitigation schemes have been proposed in literature [3,4,5]. These schemes mainly prolong device lifetime and postpone aging-related malfunctions via running the device at a lower frequency from the early stage of deployment (guardbanding), enlarging transistors (gate-sizing), leveraging partial recovery of BTI aging effects via injecting healing patterns when the device is idle [6], and so on.…”

Section: Introductionmentioning

confidence: 99%

Does Aging Matter? The Curious Case of Fault Sensitivity Analysis

Ebrahimabadi

Fadaeinia

Moradi

et al. 2022

2022 23rd International Symposium on Quality Electronic Design (ISQED)

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An adversary with physical access to a cryptographic device may place the device under an external stress such as overclocking, and under-volting in order to generate erroneous outputs based on which the keys can be retrieved. Among fault-injection attacks, Fault Sensitivity Analysis (FSA) has received considerable attention in recent years as in this attack the adversary does not need to know the faulty output; rather he/she only needs to know whether the injected fault has led to an error or not. Although fault-injection attacks, and in particular FSA, have been extensively studied in literature and a number of countermeasures have been proposed to mitigate these attacks, the impact of device aging on the success of these attacks is still an open question. Due to aging, the specifications of transistors deviate from their fabrication-time specification, leading to a change of circuit's delay over time. In this paper, we focus on the impact of aging in collision timing attacks (one of the strongest variant of FSA attacks). The corresponding results, realized by extensive HSpice simulations, show that the aging-induced impacts can facilitate such an attack. This calls for aging-resilient countermeasures that sustain the security over the lifetime of the cryptographic devices.

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Impact Study of Layout-Dependent Effects Toward FinFET Combinational Standard Cell Optimization

Wang

et al. 2023

IEEE Trans. Circuits Syst. II

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Layout-dependent aging mitigation for critical path timing

Cited by 5 publications

References 18 publications

Dealing with Aging and Yield in Scaled Technologies

Dealing with Aging and Yield in Scaled Technologies

Does Aging Matter? The Curious Case of Fault Sensitivity Analysis

Impact Study of Layout-Dependent Effects Toward FinFET Combinational Standard Cell Optimization

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