Lattice-based memory allocation

Darte, Alain; Schreiber, Rob; Villard, Gilles

doi:10.1145/951746.951749

Cited by 28 publications

(75 citation statements)

References 8 publications

(10 reference statements)

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“…Where scratchpad memories have been used within a memory hierarchy, there are examples of static analysis to determine which specific memory elements are reused. Of particular note is the work of Darte et al [5] and Liu et al [12]. These two works both explore data-reuse using a polytope model.…”

Section: Previous Workmentioning

confidence: 99%

Application Specific Memory Access, Reuse and Reordering for SDRAM

Bayliss

Constantinides

2011

Lecture Notes in Computer Science

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Abstract. The efficient use of bandwidth available on an external SDRAM interface is strongly dependent on the sequence of addresses requested. On-chip memory buffers can make possible data reuse and request reordering which together ensure bandwidth on an SDRAM interface is used efficiently. This paper outlines an automated procedure for generating an application-specific memory hierarchy which exploits reuse and reordering and quantifies the impact this has on memory bandwidth over a range of representative benchmarks. Considering a range of parameterized designs, we observe up to 50x reduction in the quantity of data fetched from external memory. This, combined with reordering of the transactions, allows up to 128x reduction in the memory access time of certain memory-intensive benchmarks.

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Section: Previous Workmentioning

confidence: 99%

Application Specific Memory Access, Reuse and Reordering for SDRAM

Bayliss

Constantinides

2011

Lecture Notes in Computer Science

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“…Also, because we are focusing on a limited class of applications, it is possible to develop a more accurate cost model. Darte has studied the general complexity of loop fusion [10] and has presented an approach for optimized memory allocation [11].…”

Section: Related Workmentioning

confidence: 99%

Practical Loop Transformations for Tensor Contraction Expressions on Multi-level Memory Hierarchies

Krishnamoorthy

Agrawal

2011

Lecture Notes in Computer Science

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Abstract. Modern architectures are characterized by deeper levels of memory hierarchy, often explicitly addressable. Optimizing applications for such architectures requires careful management of the data movement across all these levels. In this paper, we focus on the problem of mapping tensor contractions to memory hierarchies with more than two levels, specifically addressing placement of memory allocation and data movement statements, choice of loop fusions, and tile size selection. Existing algorithms to find an integrated solution to this problem even for two-level memory hierarchies have been shown to be expensive. We improve upon this work by focusing on the first-order cost components, simplifying the analysis required and reducing the number of candidates to be evaluated. We have evaluated our framework on a cluster of GPUs. Using five candidate tensor contraction expressions, we show that fusion at multiple levels improves performance, and our framework is effective in determining profitable transformations.

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“…The case of multidimensional memory storage optimisation is also interesting if we target regular loop nests for high performance codes [1,20,21]. A heuristic in case of registers is presented in [10].…”

Section: Related Workmentioning

confidence: 99%

Periodic register saturation in innermost loops

Touati

Mathe

2009

Parallel Computing

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This article treats register constraints in high performance embedded VLIW computing, aiming to decouple register constraints from instruction scheduling. It extends the register saturation (RS) concept to periodic instruction schedules, i.e., software pipelining (SWP). We formally study an approach which consists in computing the exact upper-bound of the register need for all the valid SWP schedules of an innermost loop (without overestimation), independently of the functional unit constraints. We call this upper-limit the periodic register saturation (PRS) of the data dependence graph (DDG). PRS is well adapted to situations where spilling is not a favourite solution for reducing register pressure compared to ILP scheduling: spill operations request memory data with a higher energy consumption. Also, spill code introduces unpredictable cache effects and makes Worst-Case-ExecutionTime (WCET) estimation less accurate. PRS is a computer science concept that has many possible applications. First, it provides compiler designers new ways to generate better codes regarding register optimisation by avoiding useless spilling. Second, its computation can help architectural designers to decide about the most suitable number of available registers inside an embedded VLIW processor; such architectural decision can be done with full respect to instruction level parallelism extraction, independently of the chosen functional units configuration. Third, it can be used to verify prior to instruction scheduling that a code does not require spilling. In this paper, we write an appropriate mathematical formalism for the problem of PRS computation and reduction in the case of loops where data dependence graphs may be cyclic. We prove that PRS reduction is NP-hard and we provide optimal and approximate methods. We have implemented our methods, and our experimental results demonstrate the practical usefulness and efficiency of the PRS approach.

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Lattice-based memory allocation

Cited by 28 publications

References 8 publications

Application Specific Memory Access, Reuse and Reordering for SDRAM

Application Specific Memory Access, Reuse and Reordering for SDRAM

Practical Loop Transformations for Tensor Contraction Expressions on Multi-level Memory Hierarchies

Periodic register saturation in innermost loops

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