Latest performance of ArF immersion scanner NSR-S630D for high-volume manufacturing for 7nm node

Funatsu, Takayuki; Uehara, Yusaku; Hikida, Yujiro; Hayakawa, Akira; Ishiyama, Satoshi; Hirayama, Toru; Kono, Hirotaka; Shirata, Yosuke; Shibazaki, Yuichi

doi:10.1117/12.2085735

Cited by 4 publications

(3 citation statements)

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“…9 Next is the imaging component of EPEs. We point out that overlay contributions to EPE are random, in the sense that each exposure of every cut image carries different EPE OL , but under steady-state conditions, the statistics of overlay contributions to each cut edge are the same.…”

Section: Pattern Edge Placement Errorsmentioning

confidence: 99%

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Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-8 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-10 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Section: Pattern Edge Placement Errorsmentioning

confidence: 99%

“…6 Second, overlay error is an important part of EPE. 9 In addition to exposure overlay, imaging contributes to EPEs through CD variations, directly impacting placement of the pattern edges. Total overlay budget of images projected by the scanners combines impacts of overlay and imaging.…”

Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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“…To achieve 6-DOF displacement measurement by the combination of translational sensors, it is necessary to arrange at least six measuring axes in at least three positions that are not collinear [ 10 ]. The measurement range of the grating interferometer with a single reading head is determined by the grating’s size; however, the measurement range of the grating interferometer system composed of multiple reading heads is limited by the distances between two reading heads [ 11 ]. Consider a system as shown in Figure 1 , wherein two reading heads measuring different directions are installed on the measured object with a distance d between the reading heads.…”

Section: Introductionmentioning

confidence: 99%

Grating Interferometer with Redundant Design for Performing Wide-Range Displacement Measurements

Cheng

Zhang

et al. 2022

Sensors

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Grating interferometers that use large two-dimensional grating splice modules for performing wide-range measurements have significant advantages for identifying the position of the wafer stage. However, the manufacturing process of large two-dimensional grating splice modules is very difficult. In contrast to existing redundant designs in the grating line dimension, we propose a novel interferometric reading head with a redundant design for obtaining wide-range displacement measurements. This interferometric reading head uses a one-dimensional grating splice module, and it was observed to be compatible with two orthogonal gratings. We designed a grating interferometer system composed of four reading heads to achieve a wide range of measurements and verified it using ZEMAX simulation. By conducting experiments, we were able to verify the compatibility of the reading head with gratings possessing different grating line directions; the measurement noise was found to be less than 0.3 nm.

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