Latchup in integrated circuits from energetic protons

Johnson, Arthur H.; Swift, G.M.; Edmonds, Larry D.

doi:10.1109/23.659064

Cited by 72 publications

(26 citation statements)

References 25 publications

(39 reference statements)

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“…In particular, SEE originate when an over-threshold charge is deposited in specific points, called sensible nodes, of microelectronics devices. Hence, while studying and investigating on these effects we started exploiting one of the most dangerous of the SEEs: the latchup effect [2]. This effect could be exploited as a powerful means of achieving the precise detection and positioning of a broad range of ionizing particles or, for example, the proposed device can only be used as a readout circuit for amplification and latching of a variety of signals provided by sensors.…”

Section: Introductionmentioning

confidence: 99%

Radiation detection: novel approaches and readout capabilities exploiting latchup topology via bipolar, MOSFET and MESFET transistors

Gabrielli¹,

Villani²

2010

Proceedings of 9th International Conference on Large Scale Applications and Radiation Hardness of Semiconductor Detectors — PoS

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The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the sensing capability to external sensors. The paper describes the state-of-the-art of the proposal and its development over the latest years and then the present and future studies are shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. For this, an elementary cell composed of two transistors connected in a thyristor structure is presented. Eventually, also a circuit implementing a MESFET commercial component confirms the basic principle. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchupbased cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

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Section: Introductionmentioning

confidence: 99%

Radiation detection: novel approaches and readout capabilities exploiting latchup topology via bipolar, MOSFET and MESFET transistors

Gabrielli¹,

Villani²

2010

Proceedings of 9th International Conference on Large Scale Applications and Radiation Hardness of Semiconductor Detectors — PoS

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“…If the charged particle strike induces the current within the parasitic structure, the feedback loop can amplify this current and cause it to sustain itself. The resulting high current state, known as the single event latchup, persists until the power is removed or until the device is destroyed by the high current density [4,17,18].…”

Section: Fundamental Mechanisms Of Seesmentioning

confidence: 99%

“…When fabricating CMOS circuits in the bulk technology, the parasitic n-p-n-p structures cannot be avoided unless special mitigation techniques are applied. Figure 2 shows the typical parasitic structure in CMOS integrated circuits [18]. Latchup can occur in this device because the parasitic pnp transistor, which is formed by the p+source / N-well / P-substrate, and the parasitic npn transistor, which is formed by the n+source / P-substrate / N-well, are in a feedback loop, such that the output (collector) of each transistor is connected to the input (base) of the other, as shown in the equivalent circuit depicted in Fig.…”

Section: Fundamental Mechanisms Of Seesmentioning

confidence: 99%

“…The SEL is caused by the activation of a parasitic n-p-n-p structure when a high energy particle strikes the critical region within the circuit, and it leads to the excessive current flow which could damage the circuit [4,17,18]. Thus, it is necessary to provide the sensing of the increased current consumption, shut down the power supply when the SEL is detected, and then reset the circuit to restore the normal operation.…”

Section: Introductionmentioning

confidence: 97%

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Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

et al. 2015

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The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMOS process, is presented. The SPS cell provides the latchup protection for standard cells on the principle of power domain control. It is based on a sensing/ driving PMOS transistor which acts both as a latchup sensor and a driver for the standard cells, and includes additional PMOS and NMOS transistors for controlling the sensing/ driving transistor and interfacing to the external control logic. The previous work has confirmed the SPS cell's functionality in the case of single event latchup, and the experimental investigation has proven that the SPS cell is immune to single event latchup for LET values up to 74.8 MeV cm 2 /mg. This case study extends the previous research by introducing the circuit-level simulation of the SPS cell's response to the single event transients (SETs). Using the square pulse current as a SET model, the amplitude and duration of the SET-induced voltage pulses at the SPS cell's outputs have been analyzed with respect to the injected charge, operating temperature, supply voltage, load (number of standard cells connected to the SPS cell) and sensing/driving transistor's channel width. The results have shown that the immunity of the SPS cell to SETs can be significantly enhanced by connecting a larger number of standard cells to the SPS cell and increasing the sensing/driving transistor's size, without any area overhead.An analytical expression for calculating the critical charge in terms of the transistor size and the number of standard cells connected to the SPS cell has been derived. Moreover, the SPS cell can be used as a SET sensor for detecting the levels of injected charge which cannot be mitigated by the increase of transistor size and load, and in conjunction with the external control logic it could be possible to measure the SET duration and perform online corrections of the SET-induced faults in the standard cells supplied by the SPS cell.

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“…There has been a lot of research work carried out in the past studying proton induced single event phenomenon in very large scale integration devices [5][6][7][8][9][10][11][12][13]. In this paper, we offer a simple method to estimate the saturated proton induced upset cross section for a 6T silicon-on-insulator (SOI) SRAM cell with layout and technology parameters.…”

Section: Introductionmentioning

confidence: 99%

Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

Li¹,

Zhou²,

Liu³

2012

Journal of Nuclear Science and Technology

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In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 mm technology.

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Latchup in integrated circuits from energetic protons

Cited by 72 publications

References 25 publications

Radiation detection: novel approaches and readout capabilities exploiting latchup topology via bipolar, MOSFET and MESFET transistors

Radiation detection: novel approaches and readout capabilities exploiting latchup topology via bipolar, MOSFET and MESFET transistors

Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

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