Latchup in bulk FinFET technology

Dai, Chia-Tsen; Chen, S.-H.; Linten, Dimitri; Scholz, Mirko; Hellings, Geert; Baburske, Roman; Karp, James; Hart, Michael J.; Groeseneken, G.; Ker, Ming‐Dou; Mocuta, A.; Horiguchi, N.

doi:10.1109/irps.2017.7936368

Cited by 19 publications

(3 citation statements)

References 4 publications

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“…(a) Logic area scaling metric [35] and (b) metal interconnect pitch scaling. [34] As mentioned in Subsubsection 3.2.1, there is a nonuniform potential distribution at the well boundary, and the electric field is stronger as it is closer to the boundary. With the increase of chip integration, the allowable minimum distance between MOSFET and the well boundary decreases.…”

Section: Scaling Down Of Feature Sizementioning

confidence: 94%

“…However, with the feature size scaling down and low power required in mobile applications, the supply voltage of the core circuit is usually below 1 V, which means that the latchup problem will not occur in the core circuits. [34] In addition to preventing the SEL, the guard rings, which act as taps, also inhibit the charge sharing, thus reducing the SEU cross section in DICE. [8] Therefore, for a combination of transistor location adjustment and DICE design, the guard ring cannot simply be removed, although the latchup problem is no longer a concern for the advanced Fin-FET technology.…”

Section: Feasibility Analysis 41 Tap Distributionmentioning

confidence: 99%

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Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Li¹,

Liu²,

Pei-Xiong³

et al. 2022

Chinese Phys. B

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3D TCAD simulations demonstrated that reducing the distance between the well boundary and NMOS or PMOS can mitigate the cross section of Single Event Upset (SEU) in 14 nm CMOS bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restore currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Different from Dual-interlock cells (DICE) design, under the presence of enough taps to ensure the rapid recovery of well potential, this approach is more effective under heavy ion irradiation of higher LET. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.

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Section: Scaling Down Of Feature Sizementioning

confidence: 94%

Section: Feasibility Analysis 41 Tap Distributionmentioning

confidence: 99%

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Li¹,

Liu²,

Pei-Xiong³

et al. 2022

Chinese Phys. B

View full text Add to dashboard Cite

show abstract

“…The SCR device has been reported to be useful for ESD protection in high-frequency circuits due to its higher ESD robustness within a smaller layout area and lower parasitic capacitance [22]. Besides, the SCR device can be safely used without latchup danger in advanced CMOS technologies with low supply voltage [26]. The equivalent circuit of the SCR consists of a PNP BJT and an NPN BJT, as shown in Figure 6(a).…”

Section: Esd Protection Circuit Design: Type Imentioning

confidence: 99%

Low-C ESD Protection Design in CMOS Technology

Lin¹

2019

Electrostatic Discharge - From Electrical Breakdown in Micro-Gaps to Nano-Generators

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Electrostatic discharge (ESD) protection design is needed for integrated circuits in CMOS technology. The choice for ESD protection devices in the CMOS technology includes diode, MOSFET, and silicon controlled rectifier (SCR). These ESD protection devices cause signal losses at high-frequency input/output (I/O) pads due to the parasitic capacitance. To minimize the impacts from ESD protection circuit on high-frequency performances, ESD protection circuit at I/O pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for high-frequency applications in CMOS technology is presented in this chapter. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with high-frequency circuits. As the operating frequencies of high-frequency circuits increase, on-chip ESD protection designs for high-frequency applications will continuously be an important design task.

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Emerging Effects and Future Technology

2019

Integrated Circuit Design for Radiation Environments

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Latchup in bulk FinFET technology

Cited by 19 publications

References 4 publications

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Low-C ESD Protection Design in CMOS Technology

Emerging Effects and Future Technology

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