Latch-Up Prevention With Autodetector Circuit to Stop Latch-Up Occurrence in CMOS-Integrated Circuits

Jiang, Zi-Hong; Ker, Ming‐Dou

doi:10.1109/temc.2022.3202806

Cited by 2 publications

(5 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The concept of an auto-detector circuit is to sense the trigger current from the I/O pad to control the power supply [31]. Under the latch-up I-test, the latch-up trigger current injecting toward the internal circuits can be detected by adding a hole/electron detector between the I/O cells and the internal circuits.…”

Section: Auto-detector Circuit To Stop Latch-upmentioning

confidence: 99%

“…With such an innovative circuit solution, the latch-up immunity of CMOS ICs can be substantially increased, but with a short distance between the I/O cells and the blocks of internal circuits to save the chip layout area [31].…”

Section: Auto-detector Circuit To Stop Latch-upmentioning

confidence: 99%

“…To explore the advantage of the proposed auto-detector circuit [31], a CMOS digital IC with 44 pads is depicted in Fig. 15, where there are 40 I/O pads, two power pads, and two ground pads.…”

Section: Example Of Applicationmentioning

confidence: 99%

“…In this article, the active guard ring to improve latchup immunity by circuit methodology is first reviewed in Section II. In Section III, a novel auto-detector circuit to sense the trigger current injecting from the I/O cells, and then to stop latch-up current in the internal circuits for latch-up prevention, is presented [31]. Moreover, TLU (transient-induced latch-up) is more easy to cause the latchup occurrence located inside the internal circuit blocks of CMOS ICs [11], [12], [13], [14], [15], [16].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

Ker

Jiang

2023

IEEE J. Electron Devices Soc.

Self Cite

View full text Add to dashboard Cite

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.INDEX TERMS Latch-up, latch-up prevention, silicon-controlled rectifier (SCR), guard ring, active guard ring, voltage regulator, over-current detector.

show abstract

Section: Auto-detector Circuit To Stop Latch-upmentioning

confidence: 99%

Section: Auto-detector Circuit To Stop Latch-upmentioning

confidence: 99%

Section: Example Of Applicationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

Ker

Jiang

2023

IEEE J. Electron Devices Soc.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Both process-level and layout-level designs enable the devices to be protected from SEL, while neither is applicable to commercial devices that have already been designed for production [21][22][23]. For the SEL problem in commercial CMOS devices, circuit-level designs are primarily adopted [24,25], which include power off-restart, constant current source, and cold backup. The power off-restart [26][27][28] adopts power disconnection to eliminate the latch-up of the devices.…”

Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

View full text Add to dashboard Cite

Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

show abstract

Latch-Up Prevention With Autodetector Circuit to Stop Latch-Up Occurrence in CMOS-Integrated Circuits

Cited by 2 publications

References 13 publications

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Contact Info

Product

Resources

About