Latch-Up in CMOS Integrated Circuits

Prevention of Single Event Upsets in Microelectronics

“…While body ties may reduce or eliminate parasitic bipolar gain during normal operation, they do not eliminate it during single events. It may be possible to reduce or eliminate the effect of the parasitic bipolar structure by use of techniques which degrade bipolar gain such as those used in bulk MOS processes [76][77], or by going to thinner active layers i.e. fully depleted devices.…”

Methodologies for the Statistical Analysis of Memory Response to Radiation

“…A latch-up occurs when an ion-induced voltage transient in the substrate or diffusion well triggers a parasitic thyristor, leading to the sudden establishment of an intense and potentially destructive current flow between Vdd and the ground [8]. Tap cells are connections between the memory substrate (or a diffusion well) and the ground (or Vdd), which are used to lower the resistance between the substrate/well and the associated power grid, tying its potential to its reference point and effectively preventing the triggering of the parasitic thyristor [9].…”

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

“…In the early 1980s, CMOS latchup and electrostatic discharge (ESD) phenomenon of significant interest; the reason for the significant interest in CMOS latchup and ESD was driven by the fact that CMOS latchup and ESD was a significant reliability concern [3][4][5][6][7][8]. Gregory and ShaferÕs work was one of the early publications that addressed the introduction of CMOS as a mainstream technology, and the CMOS latchup problem [3].…”

“…In the early 1980s, CMOS latchup and electrostatic discharge (ESD) phenomenon of significant interest; the reason for the significant interest in CMOS latchup and ESD was driven by the fact that CMOS latchup and ESD was a significant reliability concern [3][4][5][6][7][8]. Gregory and ShaferÕs work was one of the early publications that addressed the introduction of CMOS as a mainstream technology, and the CMOS latchup problem [3]. One of the reasons that there was a growing interest was because complimentary metal oxide semiconductor (CMOS) technology, and CMOS latchup was a roadblock to mainstream introduction of CMOS technology [1][2][3][4][5][6][7][8][9].…”

“…Gregory and ShaferÕs work was one of the early publications that addressed the introduction of CMOS as a mainstream technology, and the CMOS latchup problem [3]. One of the reasons that there was a growing interest was because complimentary metal oxide semiconductor (CMOS) technology, and CMOS latchup was a roadblock to mainstream introduction of CMOS technology [1][2][3][4][5][6][7][8][9]. In the early 1980s, in many semiconductor suppliers, there was a lack of understanding, semiconductor process solutions, test structures, standards, models, simulations, design methodologies, design rules, and design checking and verification systems to address the CMOS latchup concern.…”