A novel structure for poly-Si thin film transistors (TFTs) and its fabrication method were proposed to improve I-V characteristics of the TFTs by self-aligned lightly doped drain (LDD) / offset structure fabricated by formation of sidewall on both sides of the gate electrodes. In this structure, a capping layer is used to electrically isolate the gate lines from the data lines and to control the LDD/offset length. On forming the sidewall, the gate insulator was simultaneously etched to open source/drain region on the active poly-Si layer. In this work the LDD/offset structure was achieved by using only simplified 3-mask process, eliminating typical process steps for interlayer deposition and contact hole opening.