Laser interconnection techniques for defect avoidance in large-area restructurable silicon systems

Chapman, Glenn H.

doi:10.1016/0026-2692(92)90023-t

Cited by 1 publication

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“…For this an extemal laser system makes physical, low resistance connections in the substrate between two metal bus lines, and also can cut the bus paths. The fully CMOS compatible structure, the laser diffused link[2] [7] consists of two lines of conductively doped silicon separated by a gap of 2 microns in CMOS 1.5 micron processes (see Figures 2, 3).…”

Section: Laser Post Processing Defect Avoidancementioning

confidence: 99%

Laser processes for defect correction in large area VLSI systems

Chapman

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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The post fabrication laser processing techniques of cuffing lines and forming connections is effective in removing defects and enhancing fault tolerance in larger area V U 1 circuit. Successful applications require designs which include redundant sections for substitution and the defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requires careful attention to the physical aspects of the system, including location of the defect avoidance sites and testing considerations. The resulting gains range from significant increases in smaller chip yields to signijkant expansion of useable circuit area in the large aredwafer scale region with circuit sizes greater than 25 sq. cm.

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Section: Laser Post Processing Defect Avoidancementioning

confidence: 99%

Laser processes for defect correction in large area VLSI systems

Chapman

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Self Cite

View full text Add to dashboard Cite

show abstract

Laser interconnection techniques for defect avoidance in large-area restructurable silicon systems

Cited by 1 publication

References 3 publications

Laser processes for defect correction in large area VLSI systems

Laser processes for defect correction in large area VLSI systems

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