The post fabrication laser processing techniques of cuffing lines and forming connections is effective in removing defects and enhancing fault tolerance in larger area V U 1 circuit. Successful applications require designs which include redundant sections for substitution and the defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requires careful attention to the physical aspects of the system, including location of the defect avoidance sites and testing considerations. The resulting gains range from significant increases in smaller chip yields to signijkant expansion of useable circuit area in the large aredwafer scale region with circuit sizes greater than 25 sq. cm.