LASER: A hardware/software approach to accelerate complicated loops on CGRAs

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

2022

Coarse-GrainedReconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

“…Hardware loops. Hardware loops consist of extra logic inside the CGRA to manage the iterations of the loop in order to reduce the overhead of loop control by the processor [62]- [64].…”

Section: B Control-flow Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

2022

“…It could achieve reasonable improvement in performance and energy efficiency compared to traditional inelastic and elastic CGRAs on executing irregular loops. LASER [2] is yet another hardware solution taking compiler support to accelerate nested loops and loops with nested conditionals. Compiler transforms nested loops into single-level loops with conditionals and the hardware fetches and executes the instructions from the right path at runtime.…”

Section: Related Workmentioning

confidence: 99%

“…Case studies on processor architectures [1,12,15,25] reveal that improved performance and energy efficiency can be attained when loop-specific hardware optimizations are applied. Few recent CGRA architectures have come up with such architectural modifications to better support loop execution and reported good results [2,22,24,26].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Hardware Loop Based Optimization for CGRAs

Sunny

Das

et al. 2022

J Sign Process Syst

anced performance, energy efficiency and flexibility bestowed surging popularity on Coarse Grained Reconfigurable Array (CGRA) architectures. To further improve the performance and energy efficiency, several hardware and softwarebased loop optimizations are adopted for CGRAs. In this paper, we propose a centralized hardware-based loop optimization technique to achieve better area and energy results compared to the previously implemented distributed version. Without incurring any performance degradation, area overhead against the reference architecture is reduced down to 1.5% for a 4×2 CGRA configuration. A maximum of 47.3% and an arithmetic mean of 27.2% reduction in energy consumption is attained by the centralized version of hardware loop compared to the baseline model employing software loop. Furthermore, the paper explores the co-existence of CGRA-specific hardware and software optimizations and their impact on loop efficiencies. Enhanced results are obtained by coupling loop unrolling with centralized hardware loop support. The combination allows achieving up to 68.7% reduction in energy consumption and 5.46× speed-up against the baseline model with no optimizations applied.

“…LASER [2] is another attempt to take hardware support for optimizing the loop execution. It is a hardware-software hybrid solution designed particularly for loops with imperfect nesting and random nesting of conditionals.…”

Section: Related Workmentioning

confidence: 99%

Hardware Based Loop Optimization for CGRA Architectures

Sunny

Das

Applied Reconfigurable Computing. Architectures, Tools, and Applications

et al. 2021

With the increasing demand for high performance computing in application domains with stringent power budgets, coarse-grained reconfigurable array (CGRA) architectures have become a popular choice among researchers and manufacturers. Loops are the hot-spots of kernels running on CGRAs and hence several techniques have been devised to optimize the loop execution. However, works in this direction are predominantly software-based solutions. This paper addresses the optimization opportunities at a deeper level and introduces a hardware based loop control mechanism that can support arbitrarily nested loops up to four levels. Major contributions of this work are, a lightweight Hardware Loop Block (HLB) for CGRAs that eliminates control instruction overhead of loops and an acyclic graph transformation that removes loop branches from the application CDFG. When tested on a set of kernels chosen from various application domains, the design could achieve a maximum of 1.9× and an average of 1.5× speed-up against the conventional approach. The total number of instructions executed is reduced to half for almost all the kernels with an area and power consumption overhead of 2.6% and 0.8% respectively.