Large-Scale Model of Flip-Chip Joining Defects

Abstract

A numerical model is developed for the flip chip reflow process, including many significant aspects of the joining dynamics: thermal expansion of the device and substrate; temperature-dependent substrate warpage; random variations of the solder volume with position; and global device position above the substrate. A detailed micro-model of each interconnect captures the transition from two contacting solder bumps to a single continuous solder interconnect, using a random wetting delay parameterized by the surface energy of the bumps relative to an energy scale. The model is shown to correctly fit measurements of the device position during the reflow process, and is used to study the occurrence of non-wet and bridge defects. The effects of spatial variations in the solder volume distribution on these defects is studied in details for an actual device with 12 504 interconnections, using an effective data reduction technique.

Modeling the Flip-Chip Wetting Process

“…To identify the most important optimization opportunities to eliminate nonwet and bridge defects, we finally study the influence of various parameters on their simulated rate of occurrence (Section III-B), on a real-life dataset where the distribution of solder preform volumes on the device vary with the position of the device on the wafer (due to plating variability). A similar analysis for the deterministic (nonrandom) parametric sensitivity of the occurrence of nonwet and bridge defects is presented in [11].…”