Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Asiatici, Mikhail; Ienne, Paolo

doi:10.1109/isca52012.2021.00054

Cited by 16 publications

(25 citation statements)

References 43 publications

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“…: uncertain. 2 Required programming language for development with the system; 3 Whether the system supports automated design low for developers; 4 Whether the system has been optimized for FPGAs with multiple SLRs (from Xilinx); 5 Whether the system has been optimized for HBM-enabled FPGA platforms; 6 Evaluation is based on simulation analysis (SIM) or real hardware implementation (HW); 7 Number of evaluated graph applications with the system in corresponding papers; 8 Whether the code of the system is publicly available.…”

Section: Existing Workmentioning

confidence: 99%

“…delivers an additional 2× speedup by enabling two-level caching to ForeGraph. Nevertheless, the two works above adopt the interval-shard based partitioning method and bufers both source and destination vertices, resulting in a signiicant data replication factor and heavy preprocessing overhead [3]. Moreover, these two works are simulations that are not publicly available.…”

Section: Hbm On Fpgasmentioning

confidence: 99%

“…Although vertical partitioning is adopted, edges are sorted during graph partitioning. Recently, Asiatici et al [3] explored graph processing accelerators on multi-SLR FPGAs with caches for thousands of simultaneous misses instead of minimizing the cache misses. However, the performance is worse than HitGraph [72] and ThunderGP [12] caused by bank conlicts in the proposed miss-optimized memory system.…”

Section: Hbm On Fpgasmentioning

confidence: 99%

See 2 more Smart Citations

ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS

Chen

Cheng

Tan

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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FPGA has been an emerging computing infrastructure in datacenters benefiting from fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile, graph processing has attracted tremendous interest in data analytics, and its performance is in increasing demand with the rapid growth of data. Many works have been proposed to tackle the challenges of designing efficient FPGA-based accelerators for graph processing. However, the largely overlooked programmability still requires hardware design expertise and sizable development efforts from developers. ThunderGP , an HLS-based graph processing framework on FPGAs, is hence proposed to close the gap, with which developers could enjoy high performance of FPGA-accelerated graph processing by writing only a few high-level functions with no knowledge of the hardware. ThunderGP adopts the gather-apply-scatter (GAS) model as the abstraction of various graph algorithms and realizes the model by a build-in highly parallel and memory-efficient accelerator template. With high-level functions as inputs, ThunderGP automatically explores massive resources of multiple super-logic regions (SLRs) of modern FPGA platforms to generate and deploy accelerators, as well as schedule tasks for them. While ThunderGP on DRAM-based platforms is memory bandwidth bounded, recent high bandwidth memory (HBM) brings large potentials to performance. However, the system bottleneck shifts from memory bandwidth to resource consumption on HBM-enabled platforms. Therefore, we further propose to improve resource efficiency of ThunderGP to utilize more memory bandwidth from HBM. We conduct evaluation with seven common graph applications and nineteen graphs. ThunderGP on DRAM-based hardware platforms provides 1.9 × ∼ 5.2 × improvement on bandwidth efficiency over the state-of-the-art, while ThunderGP on HBM-based hardware platforms delivers up to 5.2 × speedup over the state-of-the-art RTL-based approach. This work is open-sourced on Github at https://github.com/Xtra-Computing/ThunderGP.

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Section: Existing Workmentioning

confidence: 99%

Section: Hbm On Fpgasmentioning

confidence: 99%

Section: Hbm On Fpgasmentioning

confidence: 99%

See 1 more Smart Citation

ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS

Chen

Cheng

Tan

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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“…As a result, efficient graph processing is becoming increasingly important, especially as the amount of graph data grows [35]. Allowing efficient customization on the hardware logic to computation/memory access patterns, FPGA usually delivers better memory efficiency and energy efficiency than CPUs/G-PUs [1], [3], [4], [9], [29], [36], [50]- [52]. Furthermore, highlevel synthesis (HLS) that translates kernels written in highlevel languages to low-level RTL modules alleviates the poor programmability issue of FPGAs, providing high usability to efficient graph processing systems [4], [14], [28].…”

Section: Introductionmentioning

confidence: 99%

“…Graph processing explores the irregular structure of a graph rather than performing large numbers of computations, resulting in poor data locality and high communication to computation ratio [25], [53]. Memory 1 ReGraph is open-sourced at https://anonymous.4open.science/r/ReGraph/. bandwidth is therefore the major bottleneck to the system performance.…”

Section: Introductionmentioning

confidence: 99%

ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines

Chen¹,

Chen²,

Cao³

et al. 2022

Preprint

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The use of FPGAs for efficient graph processing has attracted significant interest. Recent memory subsystem upgrades including the introduction of HBM in FPGAs promise to further alleviate memory bottlenecks. However, modern multi-channel HBM requires much more processing pipelines to fully utilize its bandwidth potential. Existing designs do not scale well, resulting in underutilization of the HBM facilities even when all other resources are fully consumed.In this paper, we re-examined the graph processing workloads and found much diversity in processing. We also found that the diverse workloads can be easily classified into two types, namely dense and sparse partitions. This motivates us to propose a resource-efficient heterogeneous pipeline architecture. Our heterogeneous architecture comprises of two types of pipelines: Little pipelines to process dense partitions with good locality and Big pipelines to process sparse partitions with extremely poor locality. Unlike traditional monolithic pipeline designs, the heterogeneous pipelines are tailored for more specific memory access patterns, and hence are more lightweight, allowing the architecture to scale up more effectively with limited resources. In addition, we propose a model-guided task scheduling method that schedules partitions to the right pipeline types, generates the most efficient pipeline combination and balances workloads. Furthermore, we develop an automated open-source framework, called ReGraph 1 , which automates the entire development process. ReGraph outperforms state-of-the-art FPGA accelerators by up to 5.9× in terms of performance and 12× in terms of resource efficiency.

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