2018
DOI: 10.1109/jstqe.2017.2736440
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Large-Format Geiger-Mode Avalanche Photodiode Arrays and Readout Circuits

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Cited by 40 publications
(18 citation statements)
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“…In 2002, they demonstrated an FSI SPAD array wirebonded on top of a 16-channel front-end ASIC implemented in HP CMOS process [ 19 ]. Meanwhile, the MIT Lincoln Laboratory developed their proprietary 3D integration process based on silicon-on-insulator (SOI) technology, which led them to the first 3D PDC interconnected vertically using through silicon vias (TSVs) in 2006 [ 71 , 80 ]. The top layer includes an array of SPADs of 50 pitch.…”
Section: Review Of 3d Pdcmentioning
confidence: 99%
See 1 more Smart Citation
“…In 2002, they demonstrated an FSI SPAD array wirebonded on top of a 16-channel front-end ASIC implemented in HP CMOS process [ 19 ]. Meanwhile, the MIT Lincoln Laboratory developed their proprietary 3D integration process based on silicon-on-insulator (SOI) technology, which led them to the first 3D PDC interconnected vertically using through silicon vias (TSVs) in 2006 [ 71 , 80 ]. The top layer includes an array of SPADs of 50 pitch.…”
Section: Review Of 3d Pdcmentioning
confidence: 99%
“…This contrasts with the FSI scheme, where those regions overlay each other. This imposes that the BSI design be fully depleted with a low-p-type or intrinsic absorption region [80,108]. In the FSI case, the structure is narrowly depleted and the profile type (p + n or n + p) must be chosen according to the wavelength of interest, depending on whether most photons are absorbed above the depletion (p + n ) or below the junction (n + p).…”
Section: Spad Arraymentioning
confidence: 99%
“…[ 103 ] Indeed, the number of thin SPADs that can be integrated is currently limited by the electrical connections with the external electronics, even though other research groups have already started the investigation of 3D integration techniques to increase the array format up to 256 × 256 and beyond. [ 104 ] Other advantages of thin SPADs are the high count rate they can achieve (up to 160 Mcps with an afterpulsing probability lower than 5% [ 105 ] ) and the low timing jitter (down to 32 ps FWHM even for a detector diameter as large as 200 µm [ 64 ] ) that, thanks to the employment of a suitable front end circuit, [ 72 ] can be obtained also in thin SPADs having a relatively low avalanche electric field. This is indeed very important to obtain at the same time a sharp timing response and a low DCR of few cps (demonstrated for circular SPADs having 50 µm diameter and operating at ‐20°C [ 106 ] ).…”
Section: Fabrication Technologiesmentioning
confidence: 99%
“…Thin SPAD arrays have been demonstrated to date up to a format of 8 × 8, with a separation pitch of 250 µm [109]. Indeed, the number of thin SPADs that can be integrated is currently limited by the electrical connections with the external electronics, even though other research groups have already started the investigation of 3D integration techniques to increase the array format up to 256×256 and beyond [110]. Other advantages of thin SPADs are the high count rate they can achieve (up to 160 Mcps with an afterpulsing probability lower than 5% [111]) and the low timing jitter (down to 32 ps FWHM even for a detector diameter as large as 200 µm [70]) that, thanks to the employment of a suitable front end circuit [78], can be obtained also in thin SPADs having a relatively low avalanche electric field.…”
Section: Spads For Visible/nir Detectionmentioning
confidence: 99%