Laplace operator based multi-channel image filters learning

Liu, Yantao; Liu, Meng; Liu, Bin; Sun, Jingang; Liu, Xiuping

doi:10.1299/jamdsm.2016jamdsm0098

Cited by 1 publication

(1 citation statement)

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“…In future work, we will explore new models of HW/SW co-design and new acceleration methods on Multi-core SIMD CPUs (Ouyang, et al, 2016), (Zhou, et al, 2017). We will also try to extend the proposed idea and method to other areas, such as large-scale data visualization and rendering (Chen, et al, 2017), (Inui M, et al, 2016), (Kim, Kyung and Lee, 2012), (Mandachi, Usuki and Miura, 2014), (Umezu, 2013), (Zhang, et al, 2017), large-scale co-operation editing in text and geometry in Computer-Supproted Cooperation Work (Cheng, et al, 2016), (Lv, et al, 2016), (Nomaguchi,Tsutsumi and Fujita,212), large-scale 3D model interchange and retrieval in CAD (Wu, et al, 2016), (Zhang, et al, 2016), (Komoto, Kondoh and Masui, 2016), (Yeoun and Kim, 2016), (Qin, et al, 2016, (Qin, et al, 2016 , and real-time video and large HD image processing in computer vision (Li, He and Chen, 2016), (Ni, et al, 2016), (Li, He and Chen, 2017), (Li, et al, 2017), (Li, et al, 2017), (Sun, et al, 2016), (Liu, et al, 2016),…”

Section: Discussionmentioning

confidence: 99%

A GPU-based tabu search for very large hardware/software partitioning with limited resource usage

Hou

Zhou

et al. 2017

JAMDSM

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In hardware/software (HW/SW) co-design, HW/SW partitioning is the most important step since it determines which components are implemented in hardware and which are implemented in software. Since most of HW/SW partitioning problems are NP hard, heuristic methods have to be utilized to solve them, especially for the large size problems. GPU-based heuristic methods to accelerate HW/SW co-design are a promising way to reduce run time. However, the existing methods cannot deal with very large embedded applications because of GPU resource limitations. This paper presents a method to overcome the GPU resource limitations for very large partitioning while keeping a reasonable runtime. First, at the stage of computing the costs of the candidates, we propose a fast method of 2-flipping computing for very large HW/SW co-design. Our method is also general and can deal with both odd and even numbers of nodes. More importantly, our method avoids utilizing doubleprecision arithmetic units, which are scarce resources in GPU architecture. Second, since the GPU is constrained by memory limitations and the costs of candidates cannot be directly stored in the GPU's global memory, we present a time-space tradeoff strategy to break memory limitations for very large HW/SW partitioning. In this way, the following steps can be run under the constraint of GPU's memory limitations. Third, an in-place removal of infeasible solutions is proposed to reduce the overhead of global memory by half when the neighborhood is compacted. Fourth, when evaluating the tabu status of feasible candidates, we present a bitwise representation of tabu status to minimize the transfer overhead. Finally, we conduct a number of experiments. The results show that the proposed 2-flipping method of single precision data types works well. The results also demonstrate that the proposed approach expands the number of nodes of the task graph from 10,000 to 30,000 under the limitation of the GPU's global memory of 6 GB. The correlations between compression intensity and solution quality are analyzed to ensure the fairness and soundness of our method. Our work is general and can provide guidance for other applications.

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