Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing

Teich, Jürgen; Glab, Michael; Roloff, Sascha; Schröder-Preikschat, Wolfgang; Snelting, Gregor; Weichslgartner, Andreas; Wildermann, Stefan

doi:10.1109/mcsoc.2016.30

Cited by 16 publications

(14 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Non-functional requirements of applications, e.g., real-time constraints, can often be expressed in form of intervals according to the definition for the predictability of a non-functional property from [23]:…”

Section: *-Predictabilitymentioning

confidence: 99%

“…To satisfy a set of given requirements, the observable predictability intervals of the partially satisfactory implementations must be obviously reduced. In general, this can be achieved by techniques such as restricting the input space I or using approximate computing [23]. Alternatively, isolation techniques that reduce the state space Q may be applied such as the use of simpler cores, resource reservation protocols, or using invasive computing [22].…”

Section: Run-time Requirement Enforcementmentioning

confidence: 99%

“…According to [23], each requirement of an application can be either soft or hard. In case of a soft requirement, occasional violations are still considered acceptable.…”

Section: Taxonomy Of Run-time Requirement Enforcersmentioning

confidence: 99%

“…Such a hybrid approach has been implemented within the language InvadeX10, a library-based extension of the X10 programming language. In this extension, the so-called requirements [23] on non-functional execution properties, e.g., latency, may be annotated to individual applications or program segments thereof.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Teich

Mahmoody

Pourmohseni

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

Self Cite

View full text Add to dashboard Cite

A many-core architecture is typically organized as a set of so-called storage, I/O, and compute tiles which are interconnected by a Network-on-Chip (NoC) for scalability, see, e.g., Fig. 9.1. Memory and I/O tiles enable mass storage and offchip access, respectively. Each compute tile is typically organized as a multi-core or a processor array and comprises a set of processing cores, peripherals such as memories, and a network adapter which are interconnected via one or more buses. An application to be executed on the architecture is typically composed of a set of processing tasks with known data dependencies, provided as a task graph. In case of periodic applications, actor-based models of computation and languages such as ActorX10 [17] may be used for parallel programming of MPSoCs. Each application may be augmented with one or a set of requirements on specific non-functional properties of its execution, e.g., execution time, throughput, or power corridors. In the following, a mapping of an application on a given architecture corresponds to a binding of its tasks to platform cores, a routing of the data exchanged between communicating tasks, an allocation of the required processing, communication, and storage resources, and a scheduling of tasks and communications on the allocated

show abstract

Section: *-Predictabilitymentioning

confidence: 99%

Section: Run-time Requirement Enforcementmentioning

confidence: 99%

“…According to [23], each requirement of an application can be either soft or hard. In case of a soft requirement, occasional violations are still considered acceptable.…”

Section: Taxonomy Of Run-time Requirement Enforcersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Teich

Mahmoody

Pourmohseni

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Akesson et al 5 described how to make a system composable and predictable. Teich et al, 6 extended the term of predictability from bounds on temporal behavior of a program to intervals of non‐functional properties in general. The advantages of invasive computing for timing predictability on MPSoCs are discussed in the work of Roloff et al 7 In the work of Weichslgartner et al, 8 a HAM approach is presented in the context of invasive computing.…”

Section: Related Workmentioning

confidence: 99%

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

Brand

Witterauf

Sousa

et al. 2019

Concurrency and Computation

View full text Add to dashboard Cite

Summary The fulfillment of non‐functional requirements like timing or energy consumption is of utmost importance in many embedded systems and respective applications. Especially, with the introduction of multi‐core architectures, the ability to predict non‐functional execution qualities becomes more and more difficult, as multiple concurrent application programs may interfere in execution when typically sharing all the resources. In this paper, we advocate a novel parallel computing paradigm called invasive computing that allows to isolate application programs on multi‐core targets. For a presented case study of a cyber‐physical real‐time control system, we show that invasive computing enables composability that in fact allows to characterize and analyze each application program statically and independent from each other. More specifically, it is shown that a distributed object detection algorithm for controlling an inverted pendulum and implemented on a heterogeneous invasive multi‐processor SoC (MPSoC) is able to provide real‐time guarantees as well as reliability requirements on demand.

show abstract