Lane Detection Using Steerable Filters and FPGA-based Implementation

Shang, Erke; Li, Jian; An, Xiangjing; He, Hangen

doi:10.1109/icig.2011.127

Cited by 9 publications

(8 citation statements)

References 13 publications

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“…However, [2] brought new insight about how this concept could be employed in image processing applications. Since then, several works on steerable filters have been presented in the literature [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. The major advantage of steerable filters is that, most often, computing directly the response associated with a transformed version of a filter is less efficient than, equivalently, linearly combining the steering function responses.…”

Section: Introductionmentioning

confidence: 99%

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Efficient steerable circular harmonic functions

Charalampidis

2015

Pattern Recognition

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Section: Introductionmentioning

confidence: 99%

“…In [11], the singular value decomposition (SVD) approach for obtaining steering filters is modified so that only SVDs of small matrices is required. Hardware implementations [12][13][14] may also be included in this third category. The proposed work mainly belongs to the third category.…”

Section: Introductionmentioning

confidence: 99%

Efficient steerable circular harmonic functions

Charalampidis

2015

Pattern Recognition

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“…However, as indicated previously, most of these are partial systems with the exception of the full system implemented in [5]. For example, in [9] lane detection is implemented using steerable filters on an FPGA platform. However, this is only the lane feature extraction module of a comprehensive and robust lane analysis method called VioLET in [6].…”

Section: Lane Analysis and Embedded Visionmentioning

confidence: 99%

“…However, as pointed by Stein in [11] titled, "The challenge of putting vision algorithms into a car", there is a need to explore lane analysis approaches for embedded realization. Attempts have been made to realize embedded solutions for lane estimation and tracking [9,5] etc. but as indicated in [5], most of them have been architectural translations of some parts of existing lane detection algorithms.…”

Section: Role Of Lane Analysis In Idasmentioning

confidence: 99%

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Vision-Based Lane Analysis: Exploration of Issues and Approaches for Embedded Realization

Satzoda

Trivedi

2013

2013 IEEE Conference on Computer Vision and Pattern Recognition Workshops

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An efficient circuit for error reduction in logarithmic multiplication for filtering applications

Joginipelly¹,

Charalampidis

2020

Circuit Theory & Apps

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Real-time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most timeconsuming steps of the filtering operation. Log-based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log-based hardware multipliers by appropriately altering the filter weights and without increasing the required resources. | INTRODUCTIONFiltering is a computationally expensive but widely used operation in image and signal processing applications including image enhancement, 1 smoothing, 2,3 and edge detection. 4 Hardware filtering implementations often have high circuitry and power consumption requirements, mainly due to the use of multipliers. Log-based multipliers convert multiplications and divisions to more efficient operators, namely, additions and subtractions, at the expense of accuracy.Mitchell 5 first proposed a method for implementing log-based multipliers using a piecewise linear approximation technique. Although the log and anti-log functions in Mitchell method are hardware efficient, they produce large average errors. Attempts have been made to improve Mitchell approximation by proposing several error correction circuits. These methods include Mitchell-based methods, 6-9 lookup table (LUT)-based methods, [10][11][12][13][14]19,20 and region-based approaches. [15][16][17][18][19][20][21] This work concentrates on filtering (convolution) applications, where the filter weights are known and fixed. The proposed method employs Mitchell multiplier but optimizes the filter weights so that the convolution error is reduced. Before presenting the proposed method, some background information about existing log-based multipliers is provided. | REVIEW OF LOGARITHMIC MULTIPLIERS | Mitchell logarithmic multiplierMitchell multiplier 5 uses a piecewise linear approximation of the log 2 (N) curve, as shown in Figure 1 for an integer N. The method is exact when N is a power of 2.The binary representation of N is Abbreviations: FF, flip flop; FPGA, field programmable gate array; IM, iterative log multiplier; LUT, lookup table; OD, operand decomposition.

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Lane Detection Using Steerable Filters and FPGA-based Implementation

Cited by 9 publications

References 13 publications

Efficient steerable circular harmonic functions

Efficient steerable circular harmonic functions

Vision-Based Lane Analysis: Exploration of Issues and Approaches for Embedded Realization

An efficient circuit for error reduction in logarithmic multiplication for filtering applications

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