Lamp: a tool suite for families of FPGA-based computational accelerators

Court, Tom Van; Herbordt, Martin C.

doi:10.1109/fpl.2005.1515797

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…Our methods followed standard FPGA design procedures, and were implemented primarily using the VHSIC Hardware Description Language (VHDL) supported by our LAMP tool suite. 4 We selected these methods for their ease of visualization; they are neither exhaustive nor disjoint. In addition, we avoided low-level issues related to logic design and synthesis in electronic design automation, as well as high-level issues such as partitioning and scheduling in parallel processing.…”

Section: Avoiding Implementational Heatmentioning

confidence: 99%

“…These methods differ from the others in that they require design tools not widely in use, either because they are currently proprietary 11 or exist only as prototypes. 4 Method 11: Create families of applications, not point solutions HPC applications are often complex and highly parameterized, resulting in variations in applied algorithms as well as data format. Contemporary object-oriented technology can easily support these variations, including function parameterization.…”

Section: System and Integration Issuesmentioning

confidence: 99%

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Achieving High Performance with FPGA-Based Computing

et al. 2007

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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

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Section: Avoiding Implementational Heatmentioning

confidence: 99%

Section: System and Integration Issuesmentioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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Sizing of Processing Arrays for FPGA-Based Computation

VanCourt

Herbordt

2006

2006 International Conference on Field Programmable Logic and Applications

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Computing applications in FPGAs are commonly built from repetitive structures of computing and/or memory elements. In many cases, application performance depends on the degree of parallelism -ideally, the most that will fit into the fabric of the FPGA being used. Several factors complicate determination of the largest structure that will fit the FPGA: arrays that grow polynomially and trees that grow exponentially, coupled structures that grow in different polynomial order, multiple design parameters controlling different aspects of the computing structure, and interlocked usage of different hardware resources. Combined with resource usage that depends on application-specific data elements and arithmetic details, these factors defeat any simple approach for scaling the computing structures up to the FPGA's capacity. We present an analytic framework for maximizing FPGA utilization, including features for efficient exploration of array size alternatives. We also report on design tools containing extensions that support automated sizing of FPGA-based computation arrays.

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