LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors

Digalwar, Mayuri; Raveendran, Biju K.; Mohan, Sudeept

doi:10.1016/j.suscom.2017.06.001

Cited by 3 publications

(4 citation statements)

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“…Power Management: There are some works in the context of power management in MCSs [18], [23]- [28], [40], in which, the authors have applied DVFS to minimize energy consumption and have dropped LO-Crit tasks in HI mode (rows 1-2). Researchers in [41] give a comprehensive study in the field of power and energy-aware task scheduling in MCSs.…”

Section: Related Workmentioning

confidence: 99%

“…The problem definition and motivational example are presented in Section IV. Then, in Section V, we describe the proposed Huang'14 [18], Ali'15 [23], Taherin'18 [24], Zhang'21a [25], Zhang'21b [26] (S)-Core ✓ ✓ ˆˆ✓ ˆˆ2 Haririan'15 [27], Digalwar'17 [28] (M)-Core ✓ ✓ ˆˆ✓ ˆˆ3 Ranjbar'19 [29], Ranjbar'21 [16] (M)-Core ✓ ✓ ✓ ✓ ✓ ˆˆ4 Ranjbar'22 [15] (M)-Core ✓ ✓ ✓ ✓ ˆ✓ ˆ5 Saraswat'09 [12], Saraswat '10 [13], Liu'13 [14], Al'16 [8], Alahmad'17 [30] (M)-Core ✓ ✓ ˆˆˆˆ✓ 6 Ranjbar'20 [9], Huang'14 [7], Al'16 [3] (S)-Core ✓ ✓ ✓ ˆˆ✓ ˆ7 Zeng'16 [2], Caplan'18 [11], Rambo'21 [31] (M)-Core ✓ ✓ ˆˆˆ✓ ˆ8 Koc'19 [32], Choi'18 [33] (M)-Core ✓ ✓ ✓ ˆˆ✓ ˆ9 Huang'11 [34] (M)-Core ✓ ˆˆˆˆˆˆ✓ 10 Das'14 [35] (M)-Core…”

Section: Introductionmentioning

confidence: 99%

“…). If function LPP MC Map() maps the subset sc, Algorithm 1 tests the schedulability and updates the RPM (lines[22][23][24][25][26][27][28][29][30][31][32][33][34][35]. If map suc is set (line 22), function Calculate U MC() tests the schedulability for provided mapping (line 23).…”

mentioning

confidence: 99%

“…In this step, if the flag sche suc is Algorithm 1 Proposed approach (LPP-MC) description 1: for each core ς i,j do 2:ς i,j .R P er Ð Calculate Relipq; %Eq. p8q RP M r w,h is updated by considering the changes of u i,j and p i,j values for each core ς i,j in line[23][24][25][26][27][28][29][30]…”

mentioning

confidence: 99%

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Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems

Navardi

Ranjbar

Rohbani

et al. 2022

IEEE Open J. Circuits Syst.

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Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named Life-time Peak Power management in Mixed-Criticality systems (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.

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