LALP: A Language to Program Custom FPGA-Based Acceleration Engines

Abstract

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to R. Menotti (B) · M. M. Fernandes accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

River

“…Commonly known programming languages such as C, C++, and Java do not map easily to FPGAs. More recently, new programming languages and tools have been proposed to make FPGA programming more accessible and productive [Menotti et al 2012;Villarreal et al 2010;Nikhil 2004]. Independent of these high-level tools, we have observed compilation times of up to 16 hours and memory requirements of up to 19GB RAM for Virtex-7 FPGAs.…”

LALPC: Exploiting Parallelism from FPGAs Using C Language

“…The LALP compiler adopts a focused approach to high-level synthesis, aiming to optimize algorithms relying on time critical loops [7]. The basis of this approach is called ALP (Aggressive Loop Pipelining), a hardware scheme which adapts some of the ideas proposed in [21] for execution in FPGA platforms.…”

“…operations bit-width). After creating the signals among components, the compiler performs the scheduling and balancing steps [26]. Finally, the VHDL compiler generates files with the components and their connections.…”

“…One of the approaches presented in Section 2 is LALP (Language for Aggressive Loop Pipelining), a scheme aimed to generate hardware accelerators targeting the optimization of software loops. The technique relies on a special purpose language, and underlying hardware model specially designed to optimize the execution of pipelined loops [7].…”

LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável

“…A linguagem desenvolvida, denominada LALP 9 (Menotti et. al., 2010a), teve como objetivo permitir a programação de aceleradores eficientes, usando loop pipelining agressivamente, para que os sistemas resultantes operassem com o melhor desempenho possível, buscando sempre o melhor aproveitamento dos recursos disponíveis.…”