L-turn routing: an adaptive routing in irregular networks

Koibuchi, Michihiro; Funahashi, Akira; Jouraku, Akiya; Amano, Hideharu

doi:10.1109/icpp.2001.952084

Cited by 52 publications

(33 citation statements)

References 8 publications

(12 reference statements)

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“…Section III mentions several off-chip resilient routing algorithms, most of which use up*/down* [27] as a baseline and modify the structure of its directed graph to balance traffic and enhance performance [10,21,26]. The simplest approach, the baseline up*/down* introduced by Autonet [27] in 1991, has been implemented in many high performance interconnects, such as Myrinet, InfiniBand, and Advanced Switching.…”

Section: Are Off-chip Up*/down* Schemes Applicable On-chip?mentioning

confidence: 99%

“…Off chip networks, such as clusters and Networks-Of-Workstations, first tackled the reliability challenge of unconstrained faults. A number of resilient routing algorithms that can be applied to any irregular topology (i.e., a topology that survived after a number of random faults in network links) has been proposed in this domain, including up*/down* (introduced in Autonet) [27], segmentbased routing [23], FX routing [26], L-turn [21], and smartrouting [10]. During reconfiguration, the surviving topology is communicated to a central node, which runs the reconreliability performance area bounded faults early work [12,16], VCs [17,18,29] flooding [6,24] limited n/a n/a pattern constraints convex [9,31], L or T [9], polygons [20] limited n/a n/a unbounded faults off-chip routing [10,21,23 figuration algorithm in software.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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Abstract-Extreme transistor technology scaling is causing increasing concerns in device reliability: the expected lifetime of individual transistors in complex chips is quickly decreasing, and the problem is expected to worsen at future technology nodes. With complex designs increasingly relying on Networks-on-Chip (NoCs) for on-chip data transfers, a NoC must continue to operate even in the face of many transistor failures. Specifically, it must be able to reconfigure and reroute packets around faults to enable continued operation, i.e., generate new routing paths to replace the old ones upon a failure. In addition to these reliability requirements, NoCs must maintain low latency and high throughput at very low area budget.In this work, we propose a distributed reconfiguration solution named Ariadne, targeting large, aggressively scaled, unreliable NoCs. Ariadne utilizes up*/down* for fast routing at high bandwidth, and upon any number of concurrent network failures in any location, it reconfigures to discover new resilient paths to connect the surviving nodes. Experimental results show that Ariadne provides a 40%-140% latency improvement (when subject to 50 faults in a 64-node NoC) over other on-chip state-of-the-art fault tolerant solutions, while meeting the low area budget of on-chip routers with an overhead of just 1.97%.

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Section: Are Off-chip Up*/down* Schemes Applicable On-chip?mentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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“…While these schemes provide practical solutions, there are some notable limitations. First, since Up*/Down* routing, path selection, and LID assignment are integrated, these schemes cannot be directly applied to other dead-lock free routing schemes, such as L-turn [6], that may have better load balance properties. Second, the quality of the paths selected by these schemes may not be the best.…”

Section: Introductionmentioning

confidence: 99%

On LID assignment in infiniBand networks

Nienaber

Yuan

Duan

2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

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Abstract-To realize a path in an InfiniBand network, an address, known as Local IDentifier (LID) in the InfiniBand specification, must be assigned to the destination of the path and used in the forwarding tables of intermediate switches to direct the traffic following the path. Hence, routing in InfiniBand has two components: (1) computing all paths, and (2) assigning LIDs to destinations and using them in intermediate switches to realize the paths. We refer to the task of computing paths as path computation and the task of assigning LIDs as LID assignment. This paper focuses on the LID assignment component, whose major issue is to minimize the number of LIDs required to support a given set of paths. We prove that the problem of realizing a given set of paths with a minimum number of LIDs is NPcomplete, develop an integer linear programming formulation for this problem, design a number of heuristics that are effective and efficient in practical cases, and evaluate the performance of the heuristics through simulation. The experimental results indicate that the performance of our best performing heuristic is very close to optimal. We further demonstrate that by separating path computation from LID assignment and using the schemes that are known to achieve good performance for path computation and LID assignment separately, more effective routing schemes than existing ones can be developed.

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“…There are, however, also topology agnostic routing algorithms that do not rely on virtual channels. Prominent examples are up*/down* [12], lturn [13], smart-routing [11], and FX [6]. These algorithms have in common that they are based on turn prohibition, a methodology which avoids deadlock by prohibiting a subset of all turns in the network.…”

Section: Introductionmentioning

confidence: 99%