Kinetics of formation of silicides: A review

d’Heurle, F. M.; Gas, P.

doi:10.1557/jmr.1986.0205

Cited by 408 publications

(152 citation statements)

References 80 publications

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“…Finally, NiSi 2 nucleates at higher temperatures. 19,20 XRD 2θ-ω results for our films with initial Ni:Si thickness ratio of 2:9 and RTA temperature of 450…”

Section: Discussionmentioning

confidence: 99%

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Pacella

Mukherjee

Bulsara

et al. 2013

ECS J. Solid State Sci. Technol.

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Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/In x Ga 1-x As interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/In x Ga 1-x As yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/Al x Ga 1-x As laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices. Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth.1-3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration.A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposure of III-V materials to the CMOS sequence will cause the least disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process.Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V devic...

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“…Finally, NiSi 2 nucleates at higher temperatures. 19,20 XRD 2θ-ω results for our films with initial Ni:Si thickness ratio of 2:9 and RTA temperature of 450…”

Section: Discussionmentioning

confidence: 99%

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Pacella

Mukherjee

Bulsara

et al. 2013

ECS J. Solid State Sci. Technol.

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“…On the other hand, the motion of minority atoms requires either the coexistence of two vacancies (minority and majority) or a local destruction of the crystalline lattice. 17,18) Therefore, the majority atoms of Cu are more mobile than the minority atoms of Sn in Cu 3 Sn. In the present study, Cu 3 Sn grew between Cu and Cu 6 Sn 5 due to solid-phase reaction diffusion.…”

Section: Bonding Using Mono-sn Lmmentioning

confidence: 99%

Effect of Zinc Addition on Void Formation in Solid-Liquid Interdiffusion Bonding of Copper

et al. 2016

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Solid-liquid interdiffusion bonding of Cu was carried out at 573 K with deposited Sn and Cu lms. The effect of Zn addition to the faying surfaces was investigated to reduce Kirkendall voids. At the beginning of the reaction, molten Sn reacted with Cu to form Cu 6 Sn 5 , and Cu 3 Sn successively formed between the Cu 6 Sn 5 and the Cu. Many voids formed in the Cu 3 Sn phase, especially close to the Cu 3 Sn/Cu interface. When Zn was added in the faying surfaces, Zn was segregated near the interface of Cu/Cu 3 Sn and the grain boundaries of Cu 3 Sn. The Zn segregation inhibited diffusion of Cu due to the effect of solute drag, which also delayed growth of the Cu 3 Sn layer. As a result, the uxes of Cu and Sn via the Cu 3 Sn phase were balanced out, which reduced the Kirkendall void formation.

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“…Les mécanismes de formation en films minces des siliciures ont été très étudiés [8][9][10]. En particulier d'Heurle [9] a clairement mis en évidence que lorsque la force motrice de la réaction est suffisamment faible la cinétique de formation est contrôlée par l'étape de nucléation.…”

Section: Formation D'un Siliciure Par Réaction En Phase Solide En Filunclassified

Les siliciures de métaux de transition en microélectronique : propriétés mécaniques et contraintes induites au cours de la formation en phase solide

Thomas

2009

PlastOx 2007 - Mécanismes Et Mécanique Des Interactions Plasticité - Environnement

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Résumé. Depuis le début des années 1980, des siliciures de métaux de transition (WSi 2 , TiSi 2 , CoSi 2 , NiSi) sont utilisés comme matériaux de contact et d'interconnection dans les dispositifs de la microélectronique. Ils sont formés par diffusion réactive entre un film mince de métal et le silicium. Des contraintes importantes se développent lors de la formation de la nouvelle phase intermétallique. Ces contraintes peuvent être analysées expérimentalement par mesures de courbure et diffraction des rayons X in situ. Les études expérimentales montrent que les paramètres importants qui contrôlent le développement de ces contraintes sont : (i) la variation de volume molaire. (ii) la cinétique de croissance. (iii) le mécanisme de relaxation des contraintes. Les modèles existants permettent une description phénoménologique de l'évolution des contraintes mais une compréhension physique plus fine nécessite la connaissance des propriétés mécaniques des couches très minces de siliciures.

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Kinetics of formation of silicides: A review

Cited by 408 publications

References 80 publications

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Effect of Zinc Addition on Void Formation in Solid-Liquid Interdiffusion Bonding of Copper

Les siliciures de métaux de transition en microélectronique : propriétés mécaniques et contraintes induites au cours de la formation en phase solide

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