Kinetics Modeling of the Carbon Vacancy Thermal Equilibration in 4H-SiC

Abstract

The carbon vacancy (V C ) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of V C , elucidating the possible atomistic mechanisms that control the V C equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (C i 's) from the C-rich surface, followed by recombination with V C 's, and diffusion of V C 's towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of V C after annealing at different temperatures.

Carbon vacancy control in p+-n silicon carbide diodes for high voltage bipolar applications

“…Thus, the data in Fig. 1 supports the validity of thermodynamic equilibrium anneals employing carbon-caps for controlling the [V C ] in 4H-SiC p + n diodes, consistently with the literature data measured using Schottky diodes in thermally treated epiwafers [5][6][7][8][9][10][11][12][13][14][15][16] . Notably, the annealing step (2) applied for sample C in Fig.…”

“…Nevertheless, the additional annealing step (see sample C after 1800 + 1500 • C in figure 1) results in the V C (2−/0) intensity falling below the DLTS detection limit. Thus, the data in figure 1 supports the validity of thermodynamic equilibrium anneals employing carbon-caps for controlling the [V C ] in 4H-SiC p + n diodes, consistently with the literature data measured using Schottky diodes in thermally treated epi-wafers [5][6][7][8][9][10][11][12][13][14][15][16]. Notably, the annealing step (2) applied for sample C in figure 1 was sufficient for eliminating the V C 's in the present ∼10 µm thick epi-layer, however customized anneals might be applied as a function of the layer thickness in accordance with the simulation results in Ref.…”

“…Thus, the initial elimination of V C 's in 4H-SiC epiwafers employing one of the C i ambient methods [5][6][7][8][9][10][11][12][13][14][15][16] will not keep the epi-layer free of V C permanently -as shown in Fig. 2 -since it can be readily re-generated during any further annealing step at high temperature required for the fabrication of the bipolar devices.…”

“…Thus, dedicated efforts were undertaken to reduce the [V C ] in 4H-SiC by post-growth processing of the epi-wafers, based on injecting highly mobile carbon interstitials (C i 's) from the surface or the near surface region, to recombine with V C 's in the "bulk" of the epi-layer resulting in the V C 's annihilation, (V C + C i → ∅). Three different approaches are commonly used: (i) near surface ion implantation followed by high temperature annealing [5][6][7] , (ii) thermal oxidation of the Si-terminated 4H-SiC surface [8][9][10][11][12] and (iii) annealing the 4H-SiC wafers at moderate temperature ≤1500 • C under C-rich surface conditions (carbon cap) to establish a thermodynamic equilibrium of V C [13][14][15][16] . The target was to keep the [V C ] ≤ 10 11 cm −3 which could enable sufficiently long lifetimes.…”

“…(2) thermal oxidation of the Si-terminated 4H-SiC surface [8][9][10][11][12] and (3) annealing the 4H-SiC wafers at moderate temperature ≤1500 • C under C-rich surface conditions (carbon cap) to establish a thermodynamic equilibrium of V C [13][14][15][16]. The target was to keep the [V C ] ⩽ 10 11 cm −3 which could enable sufficiently long lifetimes.…”