2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics 2007
DOI: 10.1109/cadcg.2007.4407952
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Key Problems on Network-on-Chip

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Cited by 4 publications
(2 citation statements)
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“…There have been many architectural and theoretical studies on NoCs such as design methodology [2], topology exploration [3], quality-of-service (QoS) guarantee [4], resource management by software [5], and test and verifications [6]. NoC involves in many problems ranging f rom physical layer to application layer, paper [7] will focus on the key problems for NoC. Paper [8] introduced a survey on main research topics in the area of NoC topology and gave the classification of NoC topology, discussed each specific topology in detail.A suitable NoC is an integral part of any SoC.…”
Section: System-on-chipmentioning
confidence: 99%
“…There have been many architectural and theoretical studies on NoCs such as design methodology [2], topology exploration [3], quality-of-service (QoS) guarantee [4], resource management by software [5], and test and verifications [6]. NoC involves in many problems ranging f rom physical layer to application layer, paper [7] will focus on the key problems for NoC. Paper [8] introduced a survey on main research topics in the area of NoC topology and gave the classification of NoC topology, discussed each specific topology in detail.A suitable NoC is an integral part of any SoC.…”
Section: System-on-chipmentioning
confidence: 99%
“…A long time, the in MCNP geometric modeling process, the input INP file is very cumbersome, the process is: the information part → gate card → surface cards → data card. This text expression is abstract, and error-prone, difficult to detect and correct errors [1,2]. So, how to effectively use CAD technology improve the geometric modeling efficiency of the Monte Carlo calculation procedure need to solve.…”
Section: Introductionmentioning
confidence: 99%