Key Issues for Implementing Smart Polishing in Semiconductor Failure Analysis

Abstract

Abstract"Industry 4.0" has become the future direction of manufacturing industry. To prepare for this upgrade, it is important to study the automation of semiconductor failure analysis. In this paper, the sample polishing activity was studied for upgrading to a smart polishing process. Two major issues were identified in implementing the smart polishing process: the optimization of current polishing recipes and the capability of making decisions based on live feedback. With the help of Solver add-in, the current polishing recipes were optimized. To make decisions based on live images captured during polishing, strategies were explored based on finger polishing process study. Our investigation showed that a grey scale line profile analysis on images can be used to build the vision capability of our smart polishing system, on which a decisionmaking capability can be developed.

Advanced Physical Failure Analysis Techniques for Rescuing Damaged Samples with Cracks, Scratches, or Unevenness in Delayering

“…Delayering by finger polishing is one of the commonly used physical failure analysis (PFA) techniques in the failure analysis (FA) labs. This technique is simple, direct, and flexible, which is basically mechanical polishing using fingers to press the sample against a rotating cloth plate with polishing slurry in between the cloth and the sample [1]. Before the polishing of each layer, reactive ion etch (RIE) is usually used to expose the metal structure by removing the inter-metal dielectric (IMD) for a faster removal rate and a more even surface of the polished sample.…”