Key Factors Analysis and Design Optimization of RF Direct Sampling Receiver

Wang, Xiaoya; Zheng, Jianshu; Zhang, Haiying

doi:10.1109/icct.2018.8600078

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2021

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“…Direct-RF sampling data converters [1,2,3,4,5] simplifies transceiver systems by eliminating frequency conversion stages. For multi-GHz signal sampling, phase noise (PN) of the clock signal generated from the frequency synthesizer has a significant effect on the noise performance of data converters [6,7].…”

Section: Introductionmentioning

confidence: 99%

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Li¹,

Wang²,

Wang³

et al. 2021

IEICE Electron. Express

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This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm 2 . By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

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