Key extraction from the primary side of a switched-mode power supply

Saab, Sami; Leiserson, Andrew; Tunstall, Michael

doi:10.1109/asianhost.2016.7835563

Cited by 6 publications

(5 citation statements)

References 14 publications

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“…Both signals separately had low-noise but the interference reduced the SNR of the signal of interest. As the interference contained overlapping frequencies with the signal of interest, a wavelet based detrending scheme, as used in [39], provided an effective and efficient approach for separation. After trying various wavelets, ones with a lower number of vanishing moments provided better results, indicating the need for a fast response to sudden changes in the interference [15,41].…”

Section: Experimental Outlinementioning

confidence: 99%

SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip

Longo

Mulder

Page

et al. 2015

Lecture Notes in Computer Science

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Increased complexity in modern embedded systems has presented various important challenges with regard to side-channel attacks. In particular, it is common to deploy SoC-based target devices with high clock frequencies in security-critical scenarios; understanding how such features align with techniques more often deployed against simpler devices is vital from both destructive (i.e., attack) and constructive (i.e., evaluation and/or countermeasure) perspectives. In this paper, we investigate electromagnetic-based leakage from three different means of executing cryptographic workloads (including the general purpose ARM core, an on-chip co-processor, and the NEON core) on the AM335x SoC. Our conclusion is that addressing challenges of the type above is feasible, and that key recovery attacks can be conducted with modest resources.

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Section: Experimental Outlinementioning

confidence: 99%

SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip

Longo

Mulder

Page

et al. 2015

Lecture Notes in Computer Science

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“…The question of band-limited and noisy measurements being successful in attacking symmetric algorithms was demonstrated by Saab et al [SLT16]. The work of Sabb et al is highly relevant to our work, as Saab et al perform an attack against AES on the supply side of a switch-mode power supply.…”

Section: Cross-domain Power Analysis Attacksmentioning

confidence: 89%

“…It can be seen that while some entropy reduction was achieved, the overall results did not fully recover the key in 240 × 10 6 traces. The work in Saab et al [SLT16] successfully recovered a power trace from a switch-mode power supply, although the specific techniques from Saab et al also solve jitter problems that are not present in our captures.…”

Section: On-board Regulator Modementioning

confidence: 97%

On-Device Power Analysis Across Hardware Security Domains.

O’Flynn

Dewar

2019

TCHES

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Side-channel power analysis is a powerful method of breaking secure cryptographic algorithms, but typically power analysis is considered to require specialized measurement equipment on or near the device. Assuming an attacker first gained the ability to run code on the unsecure side of a device, they could trigger encryptions and use the on-board ADC to capture power traces of that hardware encryption engine.This is demonstrated on a SAML11 which contains a M23 core with a TrustZone-M implementation as the hardware security barrier. This attack requires 160 × 106 traces, or approximately 5 GByte of data. This attack does not use any external measurement equipment, entirely performing the power analysis using the ADC on-board the microcontroller under attack. The attack is demonstrated to work both from the non-secure and secure environment on the chip, being a demonstration of a cross-domain power analysis attack.To understand the effect of noise and sample rate reduction, an attack is mounted on the SAML11 hardware AES peripheral using classic external equipment, and results are compared for various sample rates and hardware setups. A discussion on how users of this device can help prevent such remote attacks is also presented, along with metrics that can be used in evaluating other devices. Complete copies of all recorded power traces and scripts used by the authors are publicly presented.

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“…Hence, the EM emissions from inductors in IVR are likely to more strongly interfere with EM emissions from the processors. Therefore, although off-chip VRs have shown to have little effect in reducing information leakage from the processor (in fact, in certain cases, off-chip VRs have shown to be a major source of leakage [30]), the same conclusion cannot be drawn for on-chip VRs. This paper for the first time presents an in-depth measurement and characterization of the effect of IVR on EM leakage from SoCs.…”

Section: Motivation and Contributionmentioning

confidence: 99%

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

Kar

Singh

Mathew

et al. 2018

IEEE J. Solid-State Circuits

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Modern high-performance as well as powerconstrained System-on-Chips (SoC) are increasingly using hardware accelerated encryption engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operation being performed by the chip. As the EM information leakage can be collected using low-cost instruments and non-invasive measurements, EM based sidechannel attacks (EMSCA) have emerged as a major threat to security of encryption engines in a SoC. This paper presents the concept of Blindsight where an high-frequency inductive voltage regulator integrated on the same chip with an encryption engine is used to increase resistance against EMSCA. High-frequency (∼100MHz) inductive integrated voltage regulators (IVR) are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the encryption engine. The measurements are performed on a prototype circuit board with a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) engine powered by a high-frequency (125MHz) R-IVR with wirebond inductor. The EM measurements are performed under two attack scenarios, one, where an adversary gains complete physical access of the target device (EMSCA with Physical Access) and the other, where the adversary is only in proximity of the device (Proximity EMSCA). The resistance to EMSCA is characterized considering a naive adversary as well as a skilled one with intelligent post-processing capabilities. In both attack modes, for a naive adversary, EM emission from a baseline IVR (B-IVR, without control loop randomization) increases EMSCA resistance compared to a standalone AES engine. However, a skilled adversary with intelligent post-processing can observe information leakage in Test Vector Leakage Assessment (TVLA) test. Subsequently, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.

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Key extraction from the primary side of a switched-mode power supply

Cited by 6 publications

References 14 publications

SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip

SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip

On-Device Power Analysis Across Hardware Security Domains.

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

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