Kernel-centric acceleration of high accuracy stereo-matching

Kenter, Tobias; Schmitz, Henning; Plessl, Christian

doi:10.1109/reconfig.2014.7032535

Cited by 3 publications

(8 citation statements)

References 13 publications

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“…The Convey platform [9] provides a shared memory space and different API functions for allocation on and movement between physical memory locations. In order to abstract these differences away from the application side, we modified and extended the memory manager presented in [11] for the Maxeler platform. An important feature of the memory manager, particularly useful during accelerator kernel development, is to support easy switching between CPU and accelerator execution of individual kernels with all required but no unnecessary data movements.…”

Section: Kernel-centric Accelerationmentioning

confidence: 99%

“…In our new extended memory manager concept, we applied these kernel annotations to both the kernels remaining on CPU and the wrappers for kernels executing on FPGAs. This goes beyond the modifications required for the methods presented in [11], where only data usage on FPGAs was indicated. The extension is however advantageous to the kernel-centric acceleration concept, because it removes the only high-level application knowledge required for the previous version, where transfers from accelerator memory back to CPU had to be initiated manually, requiring changes for each accelerator kernel that is enabled or disabled during development.…”

Section: Kernel-centric Accelerationmentioning

confidence: 99%

“…Due to the shared address space, the Convey kernel uses the original addresses, whereas the locations in Maxeler local memory are provided by the memory manager (mm.getLMem). Just like in [11], a memory region in Maxeler local memory is allocated lazily before the first usage of some data structure in this memory.…”

Section: Kernel-centric Accelerationmentioning

confidence: 99%

“…The actually utilized amount of parallelism, typically low two-digit numbers, is limited either by resource or timing limitations during synthesis (HorDiff and scanline kernels) or by the known limits of the memory interface to feed the compute pipeline (all other kernels). For details of the synthesis results and bandwidth modeling, please refer to [11]. In order to hide feedback latencies in some kernels, in addition to this explicitly utilized parallelism, we also loop through different groups of work items in different clock cycles.…”

Section: Kernel Designs For Two Fpga Platformsmentioning

confidence: 99%

“…In this work, we build closely upon a previous publication, in which most aspects of the kernel-centric acceleration of stereo matching with specialized kernels in a spatial programming language are presented [11]. Additionally, earlier work using the vector overlay [12] was heavily modified to match the functionality and kernel selection on the dataflow platform.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Kenter

Schmitz

Plessl

2015

International Journal of Reconfigurable Computing

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FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

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Section: Kernel-centric Accelerationmentioning

confidence: 99%

Section: Kernel-centric Accelerationmentioning

confidence: 99%

Section: Kernel-centric Accelerationmentioning

confidence: 99%

Section: Kernel Designs For Two Fpga Platformsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Kenter

Schmitz

Plessl

2015

International Journal of Reconfigurable Computing

Self Cite

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Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

Kaputa

Derhak

2023

IEEE Access

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Low cost imaging sensors and powerful embedded computers have taken the field of computer vision to new heights. One of the challenges that remains is to shorten the development time that it takes to target one's algorithm to hardware. This work details the steps necessary to use Model Based Design to first simulate and then to target a stereo rectification and undistortion algorithm to an embedded FPGA system on chip hardware target. This work demonstrates what the future of FPGA-based algorithm development might look like by making use of closed loop design techniques with the aid of novel Model Based Design tool flows. Hardware-abstracted constructs such as 'virtual cameras' and the capability of pulling images off the target system and feeding them back into the simulation model help to minimize discrepancies between simulation and hardware domains, ultimately reducing the total development time. The developed system is a deterministic real time and low latency implementation as it does not rely on external off chip memory as all necessary buffering is done in the internal FPGA block RAM structures. The design is capable of processing 752x480 images at pixel line rates and is easily expandable to high resolution images. The algorithm being developed is not being touted as novel, rather that it is sufficiently complex in order to demonstrate the power of the Model Based Design tool flows.

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FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors

Chen,

Zhang,

et al. 2023

2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)

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Kernel-centric acceleration of high accuracy stereo-matching

Cited by 3 publications

References 13 publications

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors

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