KAVUAKA: A Low Power Application Specific Hearing Aid Processor

A Survey on Application Specific Processor Architectures for Digital Hearing Aids

“…In [54], a streaming DSP hardware accelerator is introduced that can compute applications such as keyword recognition or other algorithms for classifications. Any of the co-processors in [19] can be disabled by clock gating, however, these operations are elementary and are often used in hearing aid applications. This also applies to the FIR filter accelerators presented in [4,51].…”

“…This also applies to the FIR filter accelerators presented in [4,51]. The accelerators presented in [4-6, 9, 25, 33, 63] are more complex and specific, because they implement complete algorithms, such as noise reduction (NR), feedback cancellation (FBC) or [40] Convolutional neural networks (CNN) and fast Fourier transform (FFT) accelerators for speech enhancement Pu et al [54] Streaming DSP for voice code word detection Gerlach et al [19] Co-processors for hyperbolic and trigonometric functions Lin et al [41] Noise reduction (NR) accelerator Lin et al [41] Multiply-accumulate (MAC) unit accelerator Lin et al [41] Fast Fourier transform (FFT) accelerator [4-6, 9, 25, 33, 63] Analysis filter bank (AFB) accelerator [4-6, 9, 25, 33, 63] Noise reduction (NR) accelerator [4-6, 9, 25, 33, 63] Feedback cancellation (FBC) accelerator [4-6, 9, 25, 33, 63] Wide dynamic range compression (WDRC) accelerator…”

“…Block diagram of a hearing aid including multiple ASIPs and hardware accelerators [19] (© 2020 IEEE. Reprinted, with permission, from [19]).…”

“…These hearing aids are either mixed-signal or analog hearing aid designs, which have on average larger feature sizes due to more restrictive design rules and greater sensitivity to noise [61]. To overcome these limitations, the authors of [19,34,48,53] propose a chip-level integration with two separate chips. Each chip is integrated with a different ASIC technology, to independently utilize the more appropriate feature size for both, the digital and the analog components of the hearing aid.…”

“…An implementation of a related noise reduction algorithms (mband) on an ASIP with hardware accelerators [33] needs 2176 cycles for computation. Parallelism at data or instruction level, or application-specific instructions [4,5,9,19,25,33,35,47,51,56] can reduce the clock frequency requirement. Accelerators are used for computing intensive tasks, where the pure software implementation on an ASIP is not feasible.…”