Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions

Vyas, Vaibhav; Jiang-Wei, Lucian; Zhou, Peng; Hu, Xuan; Friedman, Joseph S.

doi:10.1109/tc.2020.2986970

Cited by 7 publications

(5 citation statements)

References 27 publications

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“…Rushdi et al [11] Present a prominent basic digital circuit design issue using Variable-Entered Karnaugh Maps (VEKMs) with don't care notation. Vyas et al [2] Propose a procedure widely linked to asymmetric base logic function systems using Karnaugh maps and also the technique thus makes it possible to minimize spintronic and memristive logic circuits. Wang et al [12] Design a system that enhances the concept of Karnaugh maps also demonstrate the results and applications.…”

Section: Overview Of Kaurnaugh Map Toolmentioning

confidence: 99%

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Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Islam

Hussain

Sultana

et al. 2021

GUB JOURNAL OF SCIENCE AND ENGINEERING

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In computerized integrated circuits, the fundamental principle intends to avoid the multifaceted nature of the circuitry by making it as brief as attainable and minimize the expenditure. Techniques like Quine- McCluskey (QM) and Karnaugh Map (K-Map) are often used approaches of simplifying Boolean functions. This study presents a recreation framework of simplification of the Boolean capacities by the utilize of the K- Map definition for beginner-level learners. It uses the algebraic expression of the Boolean function to decrease the number of terms, generates a circuit, and does not use any redundant sets. In this way, it gets to be competent to deal with lots of parameters and minimize the computational cost. The result of the assessment is performed in this paper by contrasting it with the C- Minimizer algorithm. In computation time terms, the result appears that our comprehensive K mapping tool outflanks in current procedures, and the relative error accomplishes a lower rate of percentage (2%), which fulfills the satisfactory level. GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 7, Dec 2020 P 76-84

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Section: Overview Of Kaurnaugh Map Toolmentioning

confidence: 99%

“…Numerous studies have been conducted to simplify the Boolean expression. First of all the Boolean function is simplified by postulates and theorems in which there are no special regulations [2]. The very first approach to minimize it seems to apply theorems of postulates and many other specific manipulation techniques.…”

mentioning

confidence: 99%

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Islam

Hussain

Sultana

et al. 2021

GUB JOURNAL OF SCIENCE AND ENGINEERING

View full text Add to dashboard Cite

show abstract

“…However, it became difficult to maintain the downscaling pace due to [2]: (i) leakage wall, (ii) reliability wall, and (iii) cost wall. This implies that Moore's law will come to an end sooner or latter and, as a result, researchers have started to explore different technologies, e.g., memristors [3]- [6], graphene devices [7]- [9], and spintronics [10]- [13]. Among them, Spin Wave (SW) technology stands apart as one of the most promising due to its [14]- [18]: (i) Ultra-low energy consumption -SW computing depends on wave interference instead of charge movements, (ii) Acceptable delay, and (iii) High scalability -SW wavelengths can reach the nanometer range.…”

Section: Introductionmentioning

confidence: 99%

Spin Wave Based Approximate Computing

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits, as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications, e.g., multimedia and social media, are error-tolerant. In this paper, we propose an ultra-low energy Approximate Full Adder (AFA) and an Approximate 2-bit inputs Multiplier (AMUL). AFA consists of one Majority gate whereas AMUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate AFA's figures of merit against state-of-the-art accurate SW, 7nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 38% and 6% less energy than state-of-the-art accurate SW and 7nm CMOS FA implementations, respectively. Moreover, it saves 56% and 20% energy when compared with accurate and approximate 45nm CMOS counterparts, respectively. Furthermore, it provides 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nm CMOS and Spin-CMOS FAs whereas it exhibits 50% less error rate than the approximate DWM FA. Last but not least, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art SW and 16nm CMOS accurate and approximate designs. The evaluation results indicate that AMUL energy consumption is at least 2.8x and 2.6x smaller than the one of state-of-the-art SW and 16nm CMOS accurate and approximate designs, respectively. AMUL has an error rate of 25%, whereas the approximate CMOS multiplier has an error rate of 38%, and requires at least 64% less chip real-estate than the CMOS counterpart.

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“…While in the last decades CMOS downscaling has been able to enable high performance computing platforms required to process the information technology revolution induced huge data amount 1 , it becomes very difficult to keep the same downscaling pace due to 2 : (i) leakage wall, (ii) reliability wall, and (iii) cost wall. This predicts that Moore's law will come to the end soon and, as a result, researchers have started to explore different technologies (e.g., memristors [3][4][5][6] , graphene devices [7][8][9] , and spintronics [10][11][12][13] ) among which Spin Wave (SW) stands apart as one of the most promising due to its [14][15][16][17][18][19][20] : (i) Ultra-low energy consumption -SW computing depends on wave interference instead of charge movements. (ii) Acceptable delay.…”

Section: Introductionmentioning

confidence: 99%

Spin Wave Based Approximate Computing

Mahmoud¹,

Vanderveken²,

Ciubotaru³

et al. 2021

Preprint

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By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications are errortolerant like multimedia and social media. In this paper we propose an ultra-low energy novel Approximate Full Adder (AFA) and a 2-bit inputs Multiplier (AMUL).The approximate FA consists of one Majority gate while the approximate MUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate the approximate FA figure of merit against state-of-the-art accurate SW, 7 nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45 nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 43% and 33% less energy than state-of-the-art accurate SW and 7 nm CMOS FA, respectively, and saves 69% and 44% when compared with accurate and approximate 45 nm CMOS, respectively, and provides a 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45 nm CMOS and Spin-CMOS FA whereas it exhibits 50% less error rate than the approximate DWM FA. Furthermore, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art accurate SW and 16 nm CMOS accurate and approximate state-of-the-art designs. The evaluation results indicate that it saves at least 2x and 5x energy in comparison with the state-of-the-art SW designs and 16 nm CMOS accurate and approximate designs, respectively, and has an average error rate of 10%, while the approximate CMOS MUL has an average error rate of 12.5%, and requires at least 64% less chip real-estate.

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Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions

Cited by 7 publications

References 27 publications

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Spin Wave Based Approximate Computing

Spin Wave Based Approximate Computing

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