JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories

Ahangari, Hamzeh; Yalcin, Gulay; Öztürk, Özcan; Ünsal, Osman; Cristal, Adrián

doi:10.1109/isvlsi.2015.48

Cited by 4 publications

(17 citation statements)

References 21 publications

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“…If joiners are not activated (CTRL="L", if switches are nMOS), then the proposed structure works normally as two separated conventional 6T SRAM cells. JSRAM cell [1] is an extension of 7T/14T cell to combine four cells in a ring fashion to achieve full immunity against single bit errors by providing an auto correction mechanism (Figure 2 right). It is also capable of tolerating multiple bit upsets (MBUs).…”

Section: A Circuit Level Reliability Enhancementmentioning

confidence: 99%

Register file reliability enhancement through adjacent narrow-width exploitation

Ahangari¹,

Alouani²,

Öztürk³

et al. 2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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Abstract-Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrowwidth values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER).

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Section: A Circuit Level Reliability Enhancementmentioning

confidence: 99%

Register file reliability enhancement through adjacent narrow-width exploitation

Ahangari¹,

Alouani²,

Öztürk³

et al. 2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…Our approach tries to improve reliability of SRAM-based memories by exploiting adjacent cell values to mutually harden both bits. Two previous works, 7T/14T cell [25] and JSRAM [26], applied transistor level coupling technique to build more reliable SRAM cells. These techniques' main limitation is the loss in available memory capacity due to data redundancy in different cells.…”

Section: Ns-sram: Neighborhood Solidarity Sram a Architecturementioning

confidence: 99%

“…Simulations were performed in HSPICE simulator with 22nm predictive technology model library [27]. Transistor sizes for typical 22nm SRAM cell were chosen from [26]. In this section, first, we evaluate employing various types of elements as joiner circuit and show the improvement obtained in read and hold SNM.…”

Section: A Setupmentioning

confidence: 99%

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NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories

Alouani

Ahangari

Öztürk

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance.

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“…JLatch and JFF are two simple low-overhead circuit ideas which join together four pre-selected latches or FFs to make a single but highly robust storage element when reliability becomes a concern (e.g., in harsh environmental conditions). This work is complementary to our previous work [2], which addressed SRAM memories to be used in FPGA's BRAMs and LUTs (since both have SRAM structure [12], [13]), while the current study addresses user latches and FFs. The main contributions of this study are as follows:…”

Section: Introductionmentioning

confidence: 96%

Reconfigurable Hardened Latch and Flip-Flop for FPGAs

Ahangari¹,

Alouani²,

Öztürk³

et al. 2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flipflops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel selfcorrecting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output.

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JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories

Cited by 4 publications

References 21 publications

Register file reliability enhancement through adjacent narrow-width exploitation

Register file reliability enhancement through adjacent narrow-width exploitation

NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories

Reconfigurable Hardened Latch and Flip-Flop for FPGAs

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