Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

Bisschop, Peter De; Laenens, Bart; Iwase, Kazuya; Yao, T.; Dusa, Mircea V.; Smayling, Michael C.

doi:10.1117/12.881688

Cited by 11 publications

(5 citation statements)

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“…This is seen in Figure 3 (work from joint collaboration between IMEC and ASML -ref. 16). Considering that there can be several such critical layers in the most advanced logic devices, this can add extraordinary cost and cycle time to the manufacturing process.…”

Section: X Nm Device Requirements For Lithographymentioning

confidence: 93%

Challenges for 1x nm device manufacturing using EUVL: scanner and mask

Arnold¹

2011

SPIE Proceedings

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EUVL lithography using high resolution step and scan systems operating at 13.5nm is being inserted in leading edge production lines for memory and logic devices. These tools use mirror optics and either laser produced plasma (LPP) or discharge produced plasma (DPP) sources along with reflective reduction masks to image circuit features. These tools show their capability to meet the challenging device requirements for imaging and overlay. Next generation scanners with resolution and overlay capability to produce 1X nm (10 nm class) memory and logic devices are in preparation. Challenges remain for EUVL, the principal of which are increasing source power enabling high productivity, building a volume mask business encouraging rapid learning cycles, and improving resist performance so it is capable of sub 20nm resolution. ROADMAPSPerformance improvements and density increases continue in memory and logic devices driven by the lithographic shrink. Moore's Law can be expected to extend to 2018 at least. In Table 1 the general device roadmap for logic, DRAM, and flash memories is shown. This information is based on projections by device engineers at IMEC and ASML, and does not represent any specific company's roadmap. One can refer to excellent invited papers published at IEDM and the VLSI Symposium in recent years to get an in-depth view of likely developments in electron devices for the rest of this decade. (1,2,3) Briefly, in logic, the planar CMOS transistor will be replaced by the finFET (4) or one of its variants such as the trigate transistor (5) in order to improve device leakage and drive current at smaller feature sizes. In DRAM, the storage capacitor becomes more difficult to scale and DRAM may be replaced by other devices such as the STT MRAM (6) or the Phase Change RAM (PCRAM, 7). In flash, the floating gate device faces scaling challenges in the diminishing number of electrons that constitute a bit and cell-to-cell interference. Possible replacement devices include the BiCS-type charge trap 3D stacked memory (8) and the 3D cross-point ReRAM (9). Further cost reduction in nonvolatile memories may be achieved by 3D stacking of layers such as the crosspoint concept. Further integration of different device types using through-silicon-via (TSV) technology may come to pass (10).Lithographic shrink remains the key driver of cost reduction in almost all scenarios. Figure 1 shows the average shrink rate for each major device type as reported to ASML by its customers projected to the end of the decade. Flash memory due to its simple periodic patterns allowing full utilization of low k1 imaging and double patterning (11) has shrunk faster than other types. With more complex imaging problems, DRAM and logic have approximately the same shrink rate, with logic offset by about 18 months from DRAM. Also shown is the rate of introduction of new lithographic resolution by ASML in dry ArF, immersion ArF, and now EUV scanners to support the fabrication of these devices. 193nm immersion and multiple patterning can support 2X n...

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Section: X Nm Device Requirements For Lithographymentioning

confidence: 93%

Challenges for 1x nm device manufacturing using EUVL: scanner and mask

Arnold¹

2011

SPIE Proceedings

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“…With the delay of inserting EUV into high volume manufacturing, mature 193nm immersion lithography appears to be the most reliable option to tackle the critical layers for the next Logic nodes, such as the Metal1 (M1) layer studied in this paper [1][2][3][4][5] . Rather than using a single exposure, as in the case of EUV, several exposures are needed to overcome the Rayleigh resolution limit determined at 193i.…”

Section: Introductionmentioning

confidence: 99%

Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

et al. 2014

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A Metal1-layer (M1) patterning study is conducted on 20nm node (N20) for random-logic applications. We quantified the printability performance on our test vehicle for N20, corresponding to Poly/M1 pitches of 90/64nm, and with a selected minimum M1 gap size of 70nm. The Metal1 layer is patterned with 193nm immersion lithography (193i) using Negative Tone Developer (NTD) resist, and a double-patterning Litho-Etch-Litho-Etch (LELE) process. Our study is based on Logic test blocks that we OPCed with a combination of calibrated models for litho and for etch. We report the Overlapping Process Window (OPW), based on a selection of test structures measured after-etch. We find that most of the OPW limiting structures are EOL (End-of-Line) configurations. Further analysis of these individual OPW limiters will reveal that they belong to different types, such as Resist 3D (R3D) and Mask 3D (M3D) sensitive structures, limiters related to OPC (Optical Proximity Corrections) options such as assist placement, or the choice of CD metrics and tolerances for calculation of the process windows itself. To guide this investigation, we will consider a 'reference OPC' case to be compared with other solutions. In addition, rigorous simulations and OPC verifications will complete the after-etch measurements to help us to validate our experimental findings.

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“…After the invention 1 and development 2 of excimer lasers, their application to photolithographic purposes was rapidly adopted. 3 For more than 15 years, the electronics industry relied on ArF (193 nm) lithography for the highest resolution in computer chip manufacturing, 4,5 improving the process by using immersion lithography techniques, 6,7 and combining this with multiple patterning techniques to decrease the reachable feature size even further. 8,9 To print smaller sizes in a single step extreme ultraviolet (EUV) lithography has been introduced, which uses a wavelength of 13.5 nm.…”

Section: Introductionmentioning

confidence: 99%

Extreme Ultraviolet Photoresponse of Organotin-Based Photoresists with Borate Counteranions

Evrard,

Sadegh,

Mathew

et al. 2024

ACS Appl. Mater. Interfaces

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Organometallic tin-oxo-hydroxo cage compounds offer a promising photoresist platform for extreme ultraviolet photolithography (EUVL). Their reactivity is dominated by the facile breaking of the tin− carbon bonds upon photon or electron irradiation. As the cage is dicationic, it exists as a complex with anions for charge compensation. In the present work, we explore the n-butyltin-oxo cage with two tetrakis-(pentafluorophenyl)borate counteranions (TinPFPB). In contrast to the small counterions that are typically used, the bulky PFPB anion absorbs a substantial fraction (∼30%) of the impinging EUV radiation (13.5 nm, 92 eV), and it has its own reactivity upon photoionization. When thin films of the complex are irradiated with EUV radiation at low doses, a positive-tone development is possible, which is rather unique as all other known tin-oxo cage resists show a negative tone (cross-linking) behavior. We propose that the initial positive tone behavior is a result of the chemical modification of the Sn cluster by fragments of the borate anions. For comparison, we include the tetrakis(p-tolyl)borate anion (TB) in the study, which has similar bulkiness, and its complex with the nbutyltin-oxo cage (TinTB) shows the usual negative tone EUV resist behavior. This negative-tone behavior for our control experiment rules out a hypothesis based purely on the steric hindrance of the anion as the cause of the different EUV reactivity.

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Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

Cited by 11 publications

References 0 publications

Challenges for 1x nm device manufacturing using EUVL: scanner and mask

Challenges for 1x nm device manufacturing using EUVL: scanner and mask

Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

Extreme Ultraviolet Photoresponse of Organotin-Based Photoresists with Borate Counteranions

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