Issues of ultra shallow junction formation using sub-1 keV ion implantation

Kase, M.; Kikuchi, Y.; Kubo, Tomohiro; Niwa, H.; Fukuda, Tetsuo

doi:10.1109/iit.1999.812064

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…1) The shrinkage of the planar complementary metal-oxide-semiconductor field effect transistor (MOSFET), however, has not been aggressive enough since the control of short channel effect (SCE) becomes difficult. [2][3][4] To increase the controllability of SCE, fully depleted silicon-on-insulator (FDSOI) transistors have been strongly suggested due to their good channel controllability. 5) In this strategy, the active silicon channel region is easy to scale-down, junction depth is self-limited, and bulk punch-through phenomenon is prevented due to a buried insulator layer.…”

Section: Introductionmentioning

confidence: 99%

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Kim

Bae

et al. 2012

Jpn. J. Appl. Phys.

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An advanced method of the novel silicon-on-insulator (SOI) realization technology is proposed for the fabrication of SOI tri-gate transistors. Using the new method, 10 nm width SOI tri-gate transistors are successfully fabricated on standard Si bulk wafers, and result in excellent electrical characteristics after optimizing the processing parameters. Among others, low-cost and high manufacturability to fabricate SOI tri-gate transistors are advantages of the proposed method. Formed on the standard Si bulk wafer process, the SOI tri-gate transistors with gate length (L G) of 45 nm have reasonable threshold voltage (V TH) of 0.18 V and showed the enhanced current drivability up to 20%. They also demonstrated good short channel effect immunities: sub-threshold swing (SS) and drain induced barrier lowering (DIBL) were 70 mV/dec and 24 mV/V, respectively. Therefore, the novel method for the novel SOI realization technology proposed in this work will be one of the candidates for the scaling-down strategy in the future.

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Section: Introductionmentioning

confidence: 99%

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Kim

Bae

et al. 2012

Jpn. J. Appl. Phys.

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Simple General Purpose Ion Beam Deceleration System Using a Single Electrode Lens

Lopes¹,

Rocha²

2015

WJET

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Ion beam deceleration properties of a newly developed low-energy ion beam implantation system were studied. The objective of this system was to produce general purpose low-energy (5 to 15 keV) implantations with high current beam of hundreds of µA level, providing the most wide implantation area possible and allowing continuously magnetic scanning of the beam over the sample(s). This paper describes the developed system installed in the high-current ion implanter at the Laboratory of Accelerators and Radiation Technologies of the Nuclear and Technological Campus, Sacavém, Portugal (CTN).

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Issues of ultra shallow junction formation using sub-1 keV ion implantation

Cited by 2 publications

References 8 publications

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Simple General Purpose Ion Beam Deceleration System Using a Single Electrode Lens

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