Issues and perspectives in multilevel interconnection technology for quarter‐micron generation

Abstract

The size of elements in an integrated circuit has been reduced according to the proportional reduction scenario (scaling scenario) which has been essential in achieving high integration and high performance of Si ULSI. In this paper, the issues and perspectives in reducing the dimensions of the interconnections will be reviewed. Then the influence of the RC delay caused by interconnection resistance and capacitance which are expected to be more serious in the quarter‐micron generation on the device performance will be discussed. In addition, a new scaling scenario needed to reduce the interconnection delay in accordance with the improvement of device performance will be proposed. At the same time, a way to improve interconnection reliability in high current density, planarization techniques, and self‐aligned techniques will be discussed.

Dependence of deposition characteristics by copper chemical vapor deposition on gas flow shape

“…However, as the line length of interconnects increases, the speed will be decreased by an increasing delay (RC delay). To minimize RC delay, the resistivity of interconnects should be decreased and the dielectric constant of the interlayer oxide should be lowered [1,2]. The interconnect material will be changed from aluminum to copper for lower resistivity and for higher resistance to electromigration [35].…”

Dependence of deposition characteristics by copper chemical vapor deposition on gas flow shape

“…To minimize RC delay, the resistivity of interconnects should be decreased and the dielectric constant of the interlayer oxide should be lowered [1,2]. However, as the line length of interconnects increases, the speed will be decreased by an increasing delay (RC delay).…”