ISPD 2018 Initial Detailed Routing Contest and Benchmarks

Pin accessibility has arisen as a major issue for detailed routing due to the increased number of design rules and higher pin density of modern technology nodes. The existing literature tackles this problem across many stages of the design flow: standard-cell layout, placement optimization and routing. In our present work, we cope with the pin accessibility challenge as a pre-processing step for detailed routing. We devise five techniques to find on-track locations in which the router can access I/O pins of standard cell instances without causing design rule violations (DRVs.) We provide the algorithm complexity analyses for each of our techniques. Some of our methods tackle the complexity of checking the design rules using pessimism (i.e., they are subject to false positives). We also study the cases in which our methods are overly pessimistic and ways to overcome pessimism. Finally, we validate our techniques using the 45 and 32 nanometer designs from the ISPD 2018 contest on initial detailed routing and show that our most robust technique can find DRV-free access points for more than 99\% of the pins of the test cases in less than 5 minutes.

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“…To compare the five procedures, the results have been computed for ISPD 2018 [14] benchmarks. These results are presented in Table I.…”

Section: Resultsmentioning

confidence: 99%

“…3. We validate our techniques the 45 and 32 nanometer designs from the ISPD18 testcase suite [14] and how that we can find access points for more than 99% of the pins in most of the testcases in less than 250 seconds with our more robust technique.…”

Section: Introductionmentioning

confidence: 88%

Algorithms for Access Point Selection at Pre-Routing Stage

Danigno

Fogaça

Monteiro

et al. 2021

JICS

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“…Moreover, it requires high computational speed to which machine learning and neural networks give an excellent assistance. But, there are few issues faced in automating the SoC designs such as the presence of target specific macros, i.e., hard macros, complex connection between different functional blocks and timing constraints associated with blocks or cells for proper functionality of entire chip [17]. Floor planning is the foremost step in physical design flow where most of issues can be dissolved and can be prevented from reoccurring at the later stages where the cost of testing and Fig.…”

Section: Machine Learning In Physical Design Floor Planningmentioning

confidence: 99%

“…Floor planning is the foremost step in physical design flow where most of issues can be dissolved and can be prevented from reoccurring at the later stages where the cost of testing and Fig. 6 Different styles of macro placement [17] removing bugs would be more. This step determines the position of the preplaced and logic cells on the core of the chip, and further, it is followed by the routing and connections of those cells.…”

Section: Machine Learning In Physical Design Floor Planningmentioning

confidence: 99%

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

Bansal

Priya

2021

Mobile Computing and Sustainable Informatics

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In the past few decades, machine learning, a subset of artificial intelligence (AI), has emerged as a disruptive technology which is now being extensively used and has stretched across various domains. Among the numerous applications, one of the most significant advancements due to Machine Learning is in the field of Very Large Scale Integrated Circuits (VLSI). Further growth and improvements in this field are highly anticipated in the near future. The fabrication of thousands of transistors in VLSI is time consuming and complex which demanded the automation of design process, and hence, computer-aided design (CAD) tools and technologies have started to evolve. The incorporation of machine learning in VLSI involves the application of machine learning algorithms at different abstraction levels of VLSI CAD. In this paper, we summarize several machine learning algorithms that have been developed and are being widely used. We also have briefly discussed about how machine learning methods have transuded the layers of VLSI design process from register transfer level (RTL) assertion generation to static timing analysis (STA) with smart and efficient models and methodologies, further enhancing the quality of chip design with power, performance and area improvements and complexity and turnaround time reduction.

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“…[7] Details the importance of interconnect optimization and how its optimization is playing a pillar role in chip performance. Also, [8,9] Present more routing closure challenges.…”

Section: Introductionmentioning

confidence: 99%

A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes

Benallal¹,

Cherif²,

Chentouf³

et al. 2019

Adv. sci. technol. eng. syst. j.

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In advanced technologies nodes, starting from 28 nm to 7 nm and below, the power consumed of integrated circuits (ICs) becomes a big concern. Consequently, actual electronic design automation (EDA) tools are facing many challenges to have low power, reduced area and keep having required performance. To reach required success criteria, and because each picosecond and each picowatt counts, continuous development of new optimization technics is necessary. In this paper, we put to the experiment and analysis a new technic to reduce IC consumed power by optimizing its interconnections (nets). We propose an optimal algorithm and enhance it for a better compromise between having less consumed power and keep having a good design rout-ability. The new wire optimization technic based on an optimal choice of target nets for optimization: which is the list of nets consuming more than 80% of the total power in the interconnection without exceeding 30% of the total number of nets. Experiments on 14 test cases show an average total power saving of 5% on both dynamic and total power.

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ISPD 2018 Initial Detailed Routing Contest and Benchmarks

Cited by 44 publications

References 15 publications

Algorithms for Access Point Selection at Pre-Routing Stage

Algorithms for Access Point Selection at Pre-Routing Stage

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes

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