Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure?

Civerchia, Federico; Pelcat, Maxime; Maggiani, Luca; Kondepu, Koteswararao; Castoldi, P.; Valcarenghi, L.

doi:10.1109/tnsm.2020.2964392

Cited by 12 publications

(4 citation statements)

References 17 publications

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“…An advantage of the GPUs is their high programmability, which is comparable to standard software applications. Civerchia et al [14] have shown that this architecture is generally well suited for 5G RAN functionality. However, they observed issues regarding the latency of data transfers.…”

Section: Acceleration Approachesmentioning

confidence: 99%

User Plane Hardware Acceleration in Access Networks: Experiences in Offloading Network Functions in Real 5G Deployments

Kundel¹,

Meuser²,

Koppe³

et al. 2022

Proceedings of the Annual Hawaii International Conference on System Sciences

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Fulfilling the ambitious Quality of Service demands of today's wireless networks, especially low latency, high bandwidths and availability, is a big challenge for researchers, network architects, and operators. Each networking component on the data path between the user equipment and the destination data network, e.g., the Internet, must provide the highest performance to meet these requirements. This work demonstrates how different network elements of the user plane, describing the whole path of user traffic, can be sped up with different hardware acceleration technologies. For that, we demonstrate how to build up a 5G standalone campus network for evaluation, working end-to-end with real user equipment and open-source software components. Further, we analyze the user plane network functions of 5G networks from the radio access network to the core. Based on our real 5G setup, the practical evaluation of the analysis results shows up how the 5G user plane hardware can be accelerated best.

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Section: Acceleration Approachesmentioning

confidence: 99%

User Plane Hardware Acceleration in Access Networks: Experiences in Offloading Network Functions in Real 5G Deployments

Kundel¹,

Meuser²,

Koppe³

et al. 2022

Proceedings of the Annual Hawaii International Conference on System Sciences

View full text Add to dashboard Cite

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“…With these computing units equip with special capabilities showing more and more powerful performance in large-scale parallel computing. OpenCL by Apple [16] and CUDA by NVIDIA [17] are both heterogeneous VOLUME 11, 2023 This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.…”

Section: Introductionmentioning

confidence: 99%

Evolutionary Game Theory-Based Optimal Scheduling Strategy for Heterogeneous Computing

She

Zhao

2023

IEEE Access

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With the development of intelligent applications, simply relying on traditional single type of computing unit cannot efficiently satisfy diverse cloud requirements. The emergence of heterogeneous computing can efficiently achieve the adaptation of these intelligent applications by using different types of processing units such as Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA). However, the trade-off between profit and costs in the process of scheduling heterogeneous computing resources is also an issue worthy of attention. To address this challenge, this work establishes a heterogeneous computing resource scheduling model based on Stackelberg differential game, which includes three roles Computing Power Trading Platforms (CPTPs), Heterogeneous Computing Service Providers (HCSPs), and Heterogeneous Computing Application Providers (HCAPs). The objective is to maximize utility function of CPTPs and HCSPs subject to rental ratio, pricing strategy and energy consumption of resource scheduling, which has proved that there exists a Stackelberg Nash Equilibrium (NE) solution. The Support Vector Machine based on Artificial Fish (SVM-AF) is proposed to predict the access times of heterogeneous computing applications. In addition, the distributed iteration method and Cauchy distribution is adopted to optimize the computing price strategy and improve its convergence performance. The simulation results show that compared with other strategies, the proposed strategy can effectively improve computing revenue of user experience and while reducing energy consumption in the process of resource scheduling.

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“…E.g., an FPGAs implementing a distributed unit receiver can improve the performance even under varying computational load conditions, with optimized power consumption and less area [29]. Civerchia et al [17] studied the optimization of Open Computing Language (OpenCL) designs implementing orthogonal frequency division multiplexing module in the 5G stack on FPGA platforms. Alimohammad et al [19] proposed an implementation on FPGA of infinite impulse response models for Rayleigh fading channels.…”

Section: Introductionmentioning

confidence: 99%

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

et al. 2022

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The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

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Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure?

Cited by 12 publications

References 17 publications

User Plane Hardware Acceleration in Access Networks: Experiences in Offloading Network Functions in Real 5G Deployments

User Plane Hardware Acceleration in Access Networks: Experiences in Offloading Network Functions in Real 5G Deployments

Evolutionary Game Theory-Based Optimal Scheduling Strategy for Heterogeneous Computing

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

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