iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor

Zhang, Yiqun; Khayatzadeh, Mahmood; Yang, Kaiyuan; Saligane, Mehdi; Pinckney, Nathaniel; Alioto, Massimo; Blaauw, David; Sylvester, Dennis

doi:10.1109/jssc.2017.2749423

Cited by 67 publications

(54 citation statements)

References 15 publications

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“…To limit such overheads popular in-situ error detection and correction (EDAC) approaches were proposed that enabled operation beyond the always correct critical timing/voltage margins [4], [2], [5]. These design-centric schemes integrate special units/registers to monitor the critical long latency paths (LLPs) and either change the cycle time [4] or utilize different recovery mechanisms [2], [5] in case of detected errors. Although effective, such schemes make it difficult to meet the design constraints and may lead to large recovery overheads, especially if the activation probability of the error-prone LLPs is high [5].…”

Section: Introductionmentioning

confidence: 99%

“…These design-centric schemes integrate special units/registers to monitor the critical long latency paths (LLPs) and either change the cycle time [4] or utilize different recovery mechanisms [2], [5] in case of detected errors. Although effective, such schemes make it difficult to meet the design constraints and may lead to large recovery overheads, especially if the activation probability of the error-prone LLPs is high [5]. Other recent work has tried to exploit the operand dependent dynamic path excitation [6] in pipelined cores.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Tsiokanos

Mukhanov

Karakonstantis

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Tsiokanos

Mukhanov

Karakonstantis

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

“…In an attempt to trim down the introduced overheads, statistical static timing analysis (SSTA) tools have been introduced [6], but such tools still focus on improving the analysis and margin estimations rather than the design itself. Design-centric techniques focus on integrating extra circuits to detect any errors and either try to correct them in-situ using special flip-flops [7] or stall the pipeline and replay the failed instructions [8], [4]. Other designcentric schemes try to predict the instructions and operands that may activate the failure prone long latency paths (LLP s) [9] and provide extra clock cycle(s) for the completion of these paths.…”

mentioning

confidence: 99%

Significance-Driven Data Truncation for Preventing Timing Failures

Tsiokanos

Mukhanov

Nikolopoulos

et al. 2019

IEEE Trans. Device Mater. Relib.

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The continuous scaling of transistor sizes and the increased parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, typically designers adopt pessimistic timing margins, which are estimated under rare worst-case conditions. In this paper, we present a technique that mitigates such pessimistic margins by minimizing the number of timing failures. In particular, we propose a method that minimizes the number of long latency paths within each processor pipeline stage and constraints them in as few stages as possible. Such a method allows us not only to reduce the timing failures, but also to limit the potential errorprone locations to only few pipeline stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and truncate the bitwidth of the operands in the few remaining long latency paths by setting a number of less significant bits (LSBs) to a constant value of zero. Such a truncation may incur quality loss, but this is limited since it is applied only to the LSBs of the few operands that may activate the confined error-prone long latency paths. To evaluate the efficiency of our method, we perform post-place and route dynamic timing analysis based on real operands extracted from a variety of applications. This helps to estimate the bit error rate, while considering the data dependent path excitation. When applied to an IEEE-754 compatible double precision Floating Point Unit (FPU), the proposed approach reduces the timing failures by 216.25× on average compared to the reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45 nm process. Our results show that the path shaping alone introduces a negligible 0.25% area and 5.7% power overheads with no performance cost. Finally, we demonstrate that by combining the path shaping with aggressive operand bitwidth truncation, we enable power savings of up-to 44.7% due to the substantially reduced switching activity at minimal quality loss.

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“…The development of the Internet of Things (IoT) [1,2] has posed stringent requirements for energy-efficient integrated circuits [3,4]. Among all the low power techniques in circuit level, voltage scaling is considered to be the most effective method due to the quadratic relation between dynamic power and supply voltage [5,6]. However, voltage scaling aggravates the circuit sensitivity to process, voltage, and temperature (PVT) variations gravely, increasing the risk of timing-margin failure [7,8].…”

Section: Introductionmentioning

confidence: 99%

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

Zhu

Bai

et al. 2019

IEICE Electron. Express

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Variation poses a guard-band requirement for integrated circuit designs, which degrades performance and energy efficiency. As the voltage scales down, the circuits are more sensitive to the variation and the guard-band margin becomes unacceptable. In this paper, we propose a novel error detection and correction technique to eliminate the margin for variation. The error detection latch introduces the low overhead of only 6 transistors compared to the conventional latch. The detection and correction scheme relaxes the timing constraint for the error signal by one clock cycle by extending another latch stage next to the critical stage. The proposed technique reduces the energy per cycle by 51% with 7.6% area overhead compared to the conventional margin technique. Comparison with other works in the state of art shows the proposed technique is quite competitive.

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iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor

Cited by 67 publications

References 15 publications

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Significance-Driven Data Truncation for Preventing Timing Failures

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

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