IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs

Ban, Yongchan; Wang, Chenchen; Zeng, Jia; Kye, Jongwook

doi:10.1117/12.2258340

Cited by 2 publications

(4 citation statements)

References 4 publications

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“…We showed that the FCA current allows to minimize IR-drop in the metal lines of a high performance processor die. Therefore, it prevents performance degradation due to slow transition or failure of gates in highly power-consuming areas [7]. Furthermore, FCAs allow to relax power grid density requirements in areas with lower power consumption.…”

Section: Background On Fca Technologymentioning

confidence: 99%

“…• FCA power ensures maintaining the IR-drop across 3D MP-SoC dies under 5%, which is a typical IR-drop constraint for high performance chip design [7], and is equivalent to under 27𝑚𝑉 for the 3𝑛𝑚 technology. High FCA IR-drop reduction is due to two main factors.…”

Section: Fca Ir-drop Reduction Capabilitiesmentioning

confidence: 99%

“…In particular, growing transistor densities result in dense dynamic switching per surface unit, which in turn generates higher temperatures and exponentially growing device leakage. Furthermore, as drive currents increase, the voltage drop (IR-drop) in power grids becomes more and more critical, affecting both performance and reliability of deeply-scaled 3D MPSoCs [7].…”

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confidence: 99%

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Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Najibi

Levisse

Zapater

et al. 2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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Deeply-scaled three-dimensional (3D) Multi-Processor Systemson-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However as process nodes shrink, temperature-dependent leakage dramatically increases, and thermal and power management becomes problematic. In this context, Integrated Flow Cell Array (FCA) technology, which consists of inter-tier microfluidic channels, combines onchip electrochemical power generation and liquid cooling of 3D MPSoCs. When connected to power delivery networks (PDN) of dies, FCAs provide an additional current compensating the voltage drop (IR-drop). In this paper, we evaluate for the first time how the IR-drop reduction and cooling capabilities of FCAs scale with advanced CMOS processes. We develop a framework to quantify the system-level impact of FCAs at technology nodes from 22𝑛𝑚 to 3𝑛𝑚. Our results show that, across all considered nodes, FCAs reduce the peak temperature of a multi-core processor (MCP) and a Machine Learning (ML) accelerator by over 22°C and 35°C, respectively, compared to off-chip direct liquid cooling. Moreover, the low operation voltages and high temperatures at advanced nodes improve up to 2× FCA power generation. Hence, FCAs allow to keep the IR-drop below 5% for both the MCP and ML accelerator, saving over 10% TSV-reserved area, as opposed to using a High-Performance Computing (HPC) MPSoC liquid cooling solution.

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Section: Background On Fca Technologymentioning

confidence: 99%

Section: Fca Ir-drop Reduction Capabilitiesmentioning

confidence: 99%

mentioning

confidence: 99%

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Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Najibi

Levisse

Zapater

et al. 2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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“…Consequently, this has led to increased route congestion, which poses a hindrance to effectively reducing chip size. Furthermore, as the IR-drop in the power delivery network (PDN) becomes more severe, the demand for metal in a limited metal track resource has increased, leading to an increasingly critical shortage of route resources [3][4].…”

Section: Introductionmentioning

confidence: 99%

Application-driven optimizations of metal stack and PDN (power delivery network) using machine learning framework

Shin,

Cho,

Ban

2024

DTCO and Computational Patterning III

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Advanced technology nodes are beginning to adopt various technologies including innovations in transistor structure and MPT (Multi Patterning Technology) to achieve BEOL (Back End of Line) scaling. During DTCO (Design-Technology Co-Optimization) activity, BEOL geometries can be explored to achieve target PPA (Power-Performance-Area).PPA, wire delay per unit distance can be reduced by increasing the metal width and spacing with given metal thickness. But increasing metal width and spacing can negatively affect the performance of the design as wire track resources per unit area reduced. Strengthening PDN (Power Delivery Network) can improve IR-drop of design, but also impact by consuming BEOL resource more.In this paper, application-driven metal stack and PDN optimization using ML (Machine-Learning) technique presented to address the issue effectively. To optimize metal stack and PDN, parameters of layer sheet count per thickness, pitch, spacing, and PDN horizontal/Vertical pitches are explored by Synopsys DSO.ai ML framework.DSO.ai optimization is constrained to maximize achieved frequency while maintaining certain IR-drop target. The metal stack and PDN optimization improved +2.2% of achieved frequency while 5.5% worse IR-drop. This is better frequency improvement than +1.4% of achieved frequency while 2.5% worse IR-drop from closest space where the DTCO done by human experts.

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IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs

Cited by 2 publications

References 4 publications

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Application-driven optimizations of metal stack and PDN (power delivery network) using machine learning framework

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