Ionizing radiation damage in 65 nm CMOS technology: Influence of geometry, bias and temperature at ultra-high doses

Borghello, Giulio; Lerario, Edoardo; Faccio, F.; Koch, Henri D.; Termo, G.; Michelis, S.; Márquez, Francisco José Arenas; Palomo, F.R.; Muñoz, F.

doi:10.1016/j.microrel.2020.114016

Cited by 20 publications

(14 citation statements)

References 28 publications

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“…Some of these TTS include core CMOS devices (rated at 1.2 V) distributed into two arrays of transistors, where either the width or the length varies, allowing to test the radiation response on different transistor dimensions. TID tests up to 1 Grad (SiO 2 ) on core 1.2 V devices confirm the reliability of these transistors under irradiation, showing similar radiation response to other 65 nm technologies [3,4]. Post-irradiation high-temperature annealing revealed the presence of two well-known radiation effects: RISCE (Radiation-Induced Short Channel Effects) and RINCE (Radiation-Induced Narrow Channel Effects) [5].…”

Section: Introductionsupporting

confidence: 66%

Measurements of total ionizing dose effects in TPSCo 65 nm and influence of NMOS bulk bias

Martin

Ballabriga²,

Borghello³

et al. 2023

J. Inst.

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The CERN EP R&D WP 1.2 aims to develop state-of-art monolithic pixel detectors using modern CMOS processes. The TPSCo 65 nm process is a suitable candidate and its radiation tolerance and sensor performance are therefore being studied. The impact of the back bias on the transistor behavior has also been measured to provide the designers with accurate models. This process shows sensitivity to radiation and degradation mechanisms similar to previously studied 65 nm CMOS technologies, strongly dependent on the geometry of the transistors. This paper presents preliminary characterization results of this technology that can serve as a guideline for designers.

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Section: Introductionsupporting

confidence: 66%

Measurements of total ionizing dose effects in TPSCo 65 nm and influence of NMOS bulk bias

Martin

Ballabriga²,

Borghello³

et al. 2023

J. Inst.

Self Cite

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“…For medium-and long-term future experiments, newer CMOS processes will be used, not only because of the higher speed, density, and lower power, but also because of the limited availability in time of current technologies. One of such technology that has already been verified, also in terms of radiation hardness, is the 65 nm CMOS process [8]. Several developments of complex readout ASICs in CMOS 65 nm have already started [9][10][11] and this process will be dominant for the next 5-10 years until a newer one, probably CMOS 28 nm, will take place.…”

Section: Introductionmentioning

confidence: 99%

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

Firlej,

Fiutowski,

Idzik

et al. 2024

J. Inst.

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The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

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“…With the scaling of CMOS technologies, the reduction in gate-oxide is likely to lessen the TID induced problems, but on the contrary has increased SEE induced transients due to the lower critical charge. However, in lower feature size (sub-90 nm) dense technologies, the accumulated charges in shallow trench isolation (STI) regions still affect the device performance [24][25][26] over the course of time.…”

Section: Introductionmentioning

confidence: 99%

TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology

2022

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This article presents a comprehensive assessment of the ionizing radiation induced effects on the performance of quadrature phase LC-tank based voltage-controlled-oscillators (VCOs). Two different quadrature VCOs (QVCOs) that are capable of generating frequencies in the range of 2.5 GHz to 2.9 GHz are implemented in a commercial 65 nm bulk CMOS technology to target for harsh radiation environments like space applications and high-energy physics (HEP) experiments. Each of the QVCOs consumes 13 mW power from a 1.2 V supply. The architectures are based on the popular implementation of two different types of QVCOs: parallel-coupled QVCO (PQVCO) and super-harmonic coupled QVCO (SQVCO). The various performance metrics (oscillation frequency, quadrature phase, phase noise, frequency tuning range, and power consumption) of the two different QVCOs are evaluated with respect to a Total ionizing Dose (TID) up to a level of approximately 100 Mrad (SiO2) through X-ray irradiation. During irradiation, the electrical characterization of the samples of the prototype are performed under biased condition at room temperature. Before irradiation, the QVCOs (PQVCO and SQVCO) achieve phase noise equal to −115 dBc/Hz and −119 dBc/Hz at 1 MHz offset, resulting in figure-of-merit (FoM) of −172.2 dBc/Hz and −176.4 dBc/Hz respectively. The test-setup of the TID experiment is discussed and the results obtained are statistically analyzed in this article to perform a comparative study of the performance of the two different QVCOs and evaluate the effectiveness of the radiation hardened by design techniques (RHBDs) employed in the implementations. Post-irradiation, the overall variations of the frequencies of the oscillators are less than 1% and the change in tuning range (TR) is less than 5% as observed from the tested samples.

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Ionizing radiation damage in 65 nm CMOS technology: Influence of geometry, bias and temperature at ultra-high doses

Cited by 20 publications

References 28 publications

Measurements of total ionizing dose effects in TPSCo 65 nm and influence of NMOS bulk bias

Measurements of total ionizing dose effects in TPSCo 65 nm and influence of NMOS bulk bias

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology

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