Ion implantation in Gallium Arsenide MESFET technology

Abstract

This review emphasizes controlled shallow doping of GaAs by ion implantation and its limitations to the stae of-art GaAs IC technology. It discusses the electrical activation behavior of implanted silicon in GaAs upon subsequent capless or silicon nitride capped rapid thermal annealing (RTA). It is demonstrated that atomic U diffuses into the implanted region of GaAs during PECVD of a Si3N4 cap and the II retards the electrical activation kinetics of the implanted Si. Applications of ion implantation to achieve buried-p layers as well as isolation between neighboring devices in GaAs are also briefly discussed. I . IntroductionThe technology of digital GaAs IC circuits has undergone a rapid advancement in recent years. The use of GaAs substrates for ICs offers several advantages over Si substrates; specifically in the area where very high frequency digital and analogic circuit operations are required. Furthermore, GaAs circuits are suited lbr optoelectronic applications. Due to its inherent radiation hardness, GaAs devices are being used actively for space and military research (1-3). The differences in devices and their performances based on Si and GaAs arise from the differences in the physical properties of the two materials. For example, unlike Si, GaAs is a direct band-gap material and the latter can be grown with semi-insulating bulk conductivity. With recent advances in ciystal growth technology 4 inch diameter semi-insulating GaAs wafers with dislocation densities of < l0 crn2 can be commercially obtained. Similarly, the availability of improved dry etching, plasma enhanced chemical vapor (ICposition (PECVI)), submicron optical lithography and rapid thermal annealing equipment has made the fahilcation of advanced digital GaAs IC simpler. It has been demonstrated recently by IBM workers that data transfer between two neighoring computers can he transferred at a I Ghit/s rate (4) using GaAs MESFlT based technology. In a MESFET, the electrical conduction between the source and drain is modulated by a bias applied to the gate. The gate to channel isolation is provided by the Schottky barrier formed by the metal-semiconductor June-SPIE Vol. 1405 Fifth Congress of the Brazilian Society ofMicroelectronics (1990) / 95 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/26/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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