“…In particular, threading dislocations (TDs) emerging on the surface can drastically decrease the top layer quality, for example, by affecting the carrier mobility and lifetime in devices 6. Several techniques have been proposed for reducing the TD density, such as annealing steps,7 aspect‐ratio‐trapping (ART)8 and selective area depositions (SAD),9 or growth of buffer layers localizing plastic relaxation, such as virtual graded layers,10 low temperature silicon buffers,11 compliant substrates,12 two‐temperature epilayers13 and ion implanted substrates 14. TD densities as low as few 10 6 cm −2 for micrometer thick Ge layers have been obtained 15.…”