(Invited) Si Nanowire Technology

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels. However, it is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, due to performance concerns -such as I on /I off ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. We have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. Si Nanowire FETs have been found to have very promising characteristics with high I on /I off ratio and high drive current which could give them a strong foothold in the near future device structures.

Phonon Dispersion in 〈100〉 Si Nanowire Covered with SiO2Film Calculated by Molecular Dynamics Simulation

“…For example, it is experimentally demonstrated that thermal conductivity of Si nanowire (SiNW) is reduced by one to two decades as compared with that of bulk, resulting in a great enhancement of the figure of merit as thermoelectric material. 5 Meanwhile, the SiNW MOSFET 7,8 suffers from heat generated in the device and requires a rapid heat dissipation rate within the system. Therefore, it is required to understand and predict a realistic picture of the complicated thermal transport process in nanostructured Si, which is governed by phonons and their energy dispersion and interactions.…”

Evaluation of thermal conductivity characteristics in Si nanowire covered with oxide by UV Raman spectroscopy

“…Silicon nanowire (SiNW) is a promising candidate for nextgeneration materials such as gate-all-around field-effect transistors (FETs), [1][2][3] solar cells 4,5) and so on. Moreover, SiNW is expected to be a new material for thermoelectric devices.…”

Evaluation of controlled strain in silicon nanowire by UV Raman spectroscopy

“…Silicon nanowires (Si NWs) are promising candidates for the channel structure of next-generation transistors such as the surrounding gate field-effect transistors (FETs). [1][2][3] By adopting the Si NW structure for the surrounding gate FETs, the short-channel effect and power consumption are reduced effectively by downsizing the CMOS devices. 4,5) Moreover, Si NWs are expected to be a new thermoelectronic material with excellent performance owing to their low dimensionality.…”