2016
DOI: 10.1149/07508.0491ecst
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(Invited) Processing Technologies for Advanced Ge Devices

Abstract: With proceeding CMOS device scaling, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons (e.g. to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing). Different aspects become even more challenging w… Show more

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Cited by 4 publications
(3 citation statements)
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“…Therefore, in the presence of hydrogen passivation, Si atoms segregate at the surface [13]. Sharper (Si)Ge-to-Si transitions were indeed observed when the Si layer is grown under H-passivation conditions such as atmospheric pressure [18] and reduced pressure [19] chemical vapor deposition (CVD). Cl passivation on SiGe surface was shown to promote Si segregation [20].…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, in the presence of hydrogen passivation, Si atoms segregate at the surface [13]. Sharper (Si)Ge-to-Si transitions were indeed observed when the Si layer is grown under H-passivation conditions such as atmospheric pressure [18] and reduced pressure [19] chemical vapor deposition (CVD). Cl passivation on SiGe surface was shown to promote Si segregation [20].…”
Section: Introductionmentioning
confidence: 99%
“…The reported methodology is intended to be a general approach for investigating faceted growth under far-from-equilibrium conditions.In the last decades, materials research in different fields, such as microelectronics and photonics, has heavily focused on miniaturization. In more recent years, both the scientific and industrial interest has progressively included in mainstream materials research the development of three-dimensional (3D) heterostructures allowing for functionalization, diversification and optimization rather than the reduction of scale [1][2][3][4][5][6][7][8][9][10][11] . Patterning emerged as a powerful and straightforward technique to control the position of the 3D structures.…”
mentioning
confidence: 99%
“…3 Nonplanar, three-dimensional (3D) heterostructures such as FinFETs 4 or gate-all-around, vertical transistors 5 emerged as promising structures to maintain scaling and meet performance requirements. 3,6,7 They also allow for exploiting peculiar features that are absent in bulk-like systems such as, e.g., high surface/volume ratios, micro-and nano-strains, and composition fluctuations. Moreover, similar nanostructures such as nanowires have been proposed in a wealth of applications in the field of nanophotonics.…”
mentioning
confidence: 99%