Invited paper: System-wide fault management based on IEEE P1687 IJTAG

Abstract

Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard allows to create an efficient and regular network for handling fault detection information as well as to manage test and system resources as a system-wide background process during the system operation.

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

“…The summary of general requirements for DIN infrastructure [3] is given below: h simple and reliable h scalable and systematic h independent from the normal system functionality h operational when system itself is not functioning properly h nonintrusive during normal operation h immediate reaction on errors h support for rollback and recovery actions h diagnose and classify faults in a background process h maintain system health information.…”

“…Architecture-wise, the DIN has to provide smooth (preferably automated, plug-and-play) integration of many different instruments into the same homogeneous fault management system [3]. As the result, we define several architectural requirements for interfaces at both sides of DIN.…”

“…This will become clear after reading Section IV of this article. Figure 2 demonstrates an example of DIN implementation in a many-core SoC, which is described in more detail in [3].…”

“…In the subwavelength lithography age, the fundamental concept of design for manufacturability (DFM) shifts its emphasis from the cost-modeldriven tradeoff analysis towards ensuring system's actual manufacturability with minimum reliability requirements [3], [4]. The design for reliability (DFR) in its turn combined design for testability (DFT) and fault tolerance in the past.…”

Test standards reuse for structured and cost-efficient dependability management of system-on-chips

“…IJTAG networks were also considered by recent works in performing dependability operations, however, the focus was only on connecting fault detecting instruments and performing system-level fault diagnosis [Jut11], [Jut13], [Shi14], [Jut16], [Shi16], [Pet14], [Zad16b] and [Zad17].…”