Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017

Wu, Qinzhe; Flolid, Steven; Song, Shuang; Deng, Junyong; John, Lizy K.

doi:10.1109/iiswc.2018.8573479

Cited by 8 publications

(2 citation statements)

References 15 publications

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“…The simulator was configured to the Intel Gainestown core [27], and Table 1 provides a summary of the configuration. We utilized the Spec2017 benchmark suite [28,29] with ref inputs for our experiments. The benchmark suite encompassed applications from diverse domains, including machine learning, liquid flow simulation, vision processing, and document parsing.…”

Section: Experimental Environmentmentioning

confidence: 99%

Electromigration-Aware Memory Hierarchy Architecture

Gabbay

Mendelson

2023

JLPEA

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New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts.

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Section: Experimental Environmentmentioning

confidence: 99%

Electromigration-Aware Memory Hierarchy Architecture

Gabbay

Mendelson

2023

JLPEA

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“…Amaral et al [5] propose the Alberta Workloads for the SPEC CPU2017 benchmark suite hoping to improve the performance evaluation of techniques that rely on any type of learning, for example the formal Feedback-Directed Optimization (FDO). Additionally, in order to ameliorate large simulation times, Wu et al [27] analyze the program behavior and consequently propose simulation points [12] for the suite.…”

Section: Related Workmentioning

confidence: 99%

Memory Centric Characterization and Analysis of SPEC CPU2017 Suite

Singh

Awasthi

2019

Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering

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In this paper we provide a comprehensive, memory-centric characterization of the SPEC CPU2017 benchmark suite, using a number of mechanisms including dynamic binary instrumentations, measurements on native hardware using hardware performance counters and OS based tools.We present a number of results including working set sizes, memory capacity consumptions and, memory bandwidth utilization of various workloads. Our experiments reveal that the SPEC CPU2017 workloads are surprisingly memory intensive, with approximately 50% of all dynamic instructions being memory intensive ones. We also show that there is a large variation in the memory footprint and bandwidth utilization profiles of the entire suite, with some benchmarks using as much as 16 GB of main memory and up to 2.3 GB/s of memory bandwidth.We also perform instruction execution and distribution analysis of the suite and find that the average instruction count for SPEC CPU2017 workloads is an order of magnitude higher than SPEC CPU2006 ones. In addition, we also find that FP benchmarks of the SPEC 2017 suite have higher compute requirements: on average, FP workloads execute three times the number of compute operations as compared to INT workloads.

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