INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design

Khailany, Brucek; Krimer, Evgeni; Venkatesan, Rangharajan; Clemons, Jason; Emer, Joel; Fojtik, Matthew; Klinefelter, Alicia; Pellauer, Michael; Pinckney, Nathaniel; Shao, Yakun Sophia; Srinath, Shreesha; Torng, Christopher; Xi, Sam Likun; Zhang, Yanqing; Zimmer, Brian

doi:10.1109/dac.2018.8465897

Cited by 17 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The NoC simulator is transaction-based and cycle-exact for modeling the on-chip traffic. Leveraging the synthesizable SystemC router design from Matchlib [41] that supports unicast and multicast requests, we construct a resizable 2-D mesh network and implement an X-Y routing scheme. The simulator captures both computation and communication latencies by concurrently modeling data transfers in the NoC, the PE executions, and off-chip DRAM accesses based on the DRAMSim2 model [58], where the impact of traffic congestion on the NoC can also be manifested.…”

Section: A Evaluation Platformsmentioning

confidence: 99%

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators

Huang¹,

Kang²,

Dinh³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

Recent advances in Deep Neural Networks (DNNs) have led to active development of specialized DNN accelerators, many of which feature a large number of processing elements laid out spatially, together with a multi-level memory hierarchy and flexible interconnect. While DNN accelerators can take advantage of data reuse and achieve high peak throughput, they also expose a large number of runtime parameters to the programmers who need to explicitly manage how computation is scheduled both spatially and temporally. In fact, different scheduling choices can lead to wide variations in performance and efficiency, motivating the need for a fast and efficient search strategy to navigate the vast scheduling space.To address this challenge, we present CoSA, a constrainedoptimization-based approach for scheduling DNN accelerators. As opposed to existing approaches that either rely on designers' heuristics or iterative methods to navigate the search space, CoSA expresses scheduling decisions as a constrained-optimization problem that can be deterministically solved using mathematical optimization techniques. Specifically, CoSA leverages the regularities in DNN operators and hardware to formulate the DNN scheduling space into a mixed-integer programming (MIP) problem with algorithmic and architectural constraints, which can be solved to automatically generate a highly efficient schedule in one shot. We demonstrate that CoSA-generated schedules significantly outperform state-of-the-art approaches by a geometric mean of up to 2.5× across a wide range of DNN networks while improving the time-to-solution by 90×.

show abstract

Section: A Evaluation Platformsmentioning

confidence: 99%

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators

Huang¹,

Kang²,

Dinh³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…Therefore, it is important to use an RTL development approach that is 1) efficient, 2) minimizes bugs, and 3) is supported by front-to-back EDA tool flows. In recent years, there has been a significant research effort exploring new hardware design languages [8], [9], as well as high-level synthesis (HLS) from C++/SystemC [10]. We use SystemVerilog (SV) for most of our RTL design, which is mature, natively supported by EDA tools [11], and relatively well supported [12].…”

Section: Agile Rtl Developmentmentioning

confidence: 99%

CHIPKIT: An agile, reusable open-source framework for rapid test chip development

Whatmough,

Donato,

et al. 2020

Preprint

View full text Add to dashboard Cite

The current trend for domain-specific architectures (DSAs) has led to renewed interest in research test chips to demonstrate new specialized hardware. Tape-outs also offer huge pedagogical value garnered from real hands-on exposure to the whole system stack. However, successful tape-outs demand hard-earned experience, and the design process is time consuming and fraught with challenges. Therefore, custom chips have remained the preserve of a small number of research groups, typically focused on circuit design research. This paper describes the CHIPKIT framework. We describe a reusable SoC subsystem which provides basic IO, an on-chip programmable host, memory and peripherals. This subsystem can be readily extended with new IP blocks to generate custom test chips. We also present an agile RTL development flow, including a code generation tool called VGEN. Finally, we outline best practices for full-chip validation across the entire design cycle.

show abstract

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Umadevi,

Venkatesh

2023

Wireless Pers Commun

View full text Add to dashboard Cite

INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design

Cited by 17 publications

References 3 publications

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators

CHIPKIT: An agile, reusable open-source framework for rapid test chip development

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Contact Info

Product

Resources

About