2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition 2009
DOI: 10.1109/apec.2009.4802702
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Investigation on Via Arrangements for the Thermal Management of High Current PCBs

Abstract: Joule heating of copper traces and vias in high current PCBs can significantly deteriorate the reliability of power electronics products. Optimization of the PCB layout is therefore fundamental to guarantee the thermal performance of a converter. This paper investigates the temperature distribution of copper traces and through via holes, when number and disposition of parallel vias are changed in a standard PCB.

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Cited by 3 publications
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“…As an example, a PCB board experiences localized hot spots due to current crowding. In literature, multi-physics FEM is used to investigate how the copper thickness and placement of vias is crucial to avoid hotspots in high power PCBs [68]- [70]. Following the thermal simulation, it is possible to add mechanical parameters to the materials and solve for the thermo-mechanical induced stress.…”
Section: B Thermo-mechanical Induced Stressmentioning
confidence: 99%
“…As an example, a PCB board experiences localized hot spots due to current crowding. In literature, multi-physics FEM is used to investigate how the copper thickness and placement of vias is crucial to avoid hotspots in high power PCBs [68]- [70]. Following the thermal simulation, it is possible to add mechanical parameters to the materials and solve for the thermo-mechanical induced stress.…”
Section: B Thermo-mechanical Induced Stressmentioning
confidence: 99%