Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Abstract

Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

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“…5 The main issue in MVL structures is the decrement of noise margin due to the voltage band division between more true states. In metal-oxidesemiconductor field-effect transistor (MOSFET) implementations, MVL has suffered from lack of stability due to its weak noise immunity in sub 45 nm nodes, 6 while by several changes in the fabrication of MOSFET it can be improved for MVL implementations; for example, ternary-complementary metal-oxide-semiconductor (T-CMOS), 7,8 while in such technologies issues such as logic specification in which for aforementioned designs is ternary logic, mass product issues, and last but not the least the high cost of fabrication slowed down its progress. Other than T-CMOS, technologies such as Graphene Nano-ribbon field-effect transistor (GNRFET) and carbon Nano-tube field-effect transistor (CNFET) are being used in literature in the case of designing MVL circuits.…”