Investigation on TSV impact on 65nm CMOS devices and circuits

Chaabouni, H.; Rousseau, M.; Leduc, P.; Farcy, A.; Farhane, R. El; Thuaire, Aurélie; G., Haury; Valentian, Alexandre; Billiot, G.; Assous, M.; Crecy, F. de; Cluzel, J.; Toffoli, A.; Bouchu, D.; Cadix, L.; Lacrevaz, T.; Ancey, P.; Sillon, N.; Flechet, B.

doi:10.1109/iedm.2010.5703479

Cited by 41 publications

(11 citation statements)

References 3 publications

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“…According to the piezo-resistive behaviour of silicon, stress affects hole mobility much more than electron mobility [11]. In [2] where the devices were based on 65 nm CMOS process technology, simulated results based on ANSYS are in agreement with theory. Table 1 summaries the nMOSFET and pMOSFET I on variation reported by various foundries and research institutes based on CMOS technology, device channel length and Keep Out Zone (KOZ) used.…”

Section: Introductionsupporting

confidence: 73%

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Lee

Liu

et al. 2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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Impact caused by Through-Silicon Via (TSV) induced thermo-mechanical stress on device performance has been a concern for three-dimensional (3D) integrated circuit (IC) integration because of the close proximity of TSVs to semiconductor devices. From the literatures, there are conflicting reports between theory, simulated and experimental results. For realistic and reasonably accurate predictions, the stress build-up by taking the full CMOS process flow into consideration is simulated. We investigated various key factors such as the orientation of TSV to device, device channel length and different CMOS technologies on the impact of TSV induced thermomechanical stress on device performance. Results exhibit that TSV induced stress impacts more on long channel nMOSFETs typically used in analog applications than that on digital devices of minimum channel length for the same CMOS technology. This is mainly due to the decrease in the impact of tensile stress liner in the long channel nMOSFET. In addition, the impact of TSV induced stress on nMOSFET devices of the same channel length of 180 nm is found to be larger for 130 nm technology than 28 nm and 65 nm technologies, which resolves conflicts in past reports.

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Section: Introductionsupporting

confidence: 73%

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Lee

Liu

et al. 2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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“…In addition to this successful characterization of the 3D interconnects, continuous efforts are also being put into the evaluation of their impact on CMOS devices [7]- [9].…”

Section: Discussionmentioning

confidence: 99%

Electrical and morphological assessment of via middle and backside process technology for 3D integration

Colonna

Coudrain

Garnier

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

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“…For CMOS device wafers, the only creditable publication is given by LETI, et al, [9]. However, due to logistic and technical issues, which will be discussed in Sections (C.3) and (C.4), TSV fabricated by the via-last (from the backside) process should be avoided until these issues are resolved.…”

Section: Tsvs Fabricated By the Via-last (From The Backside) Processmentioning

confidence: 98%

Supply chains for 3D IC integration manufacturing

Lau

2012

2012 14th International Conference on Electronic Materials and Packaging (EMAP)

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Investigation on TSV impact on 65nm CMOS devices and circuits

Cited by 41 publications

References 3 publications

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Electrical and morphological assessment of via middle and backside process technology for 3D integration

Supply chains for 3D IC integration manufacturing

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